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Part: 900/H2Series
Category:
Microcontrollers
-> CISC->TMP
Description: Product Line of 32-bit Microcontrollers With Internal ROM
Company: Toshiba America Electronic Components, Inc.
Datasheet: Download 900/H2Series datasheet File size : 287 kB
Request For quote: Find where to buy 900/H2Series
Datasheet text preview:
900/H2 Series Product Line of 32-Bit Microcontrollers with Internal ROM
Seamless core 900 Family
Toshiba is now offering the TMP94CS40AF product line -- internal ROM versions of the 32-bit 900/H2 Series from the 900-Family. Thanks to its seamless core line, Toshiba provides strong support for customers developing more advanced systems.
Features
q Original high-speed 32-bit CPU core q q q q Full instruction code compatibility with 16-bit 900-Series microcontrollers High-speed instruction execution (basic instructions: one clock cycle) Internal data bus: 32 bits, external data bus: 8/16/32 bits Operating frequency: 20 MHz (basic instructions: 50 ns) Operating frequency: 24 MHz (under development) q High-speed data transfer function (micro DMA: 5 clock cycles (min)/8 channels) q 64-KB internal ROM (TMP94CS40AF) q Connectable directly to memory (DRAM controller/2 channels)
Product List
Product name Function
Embedded Embedded ROM (bytes) RAM (bytes) I/O Port Minimum Instruction Operating Execution Time Temperature (°C)
Package
Features
DA converter: 8 bits X 2 channels
5 TMP94C241AF Timer counters: 16 bits X 4 TMP94CS40AF
Timers: 8 bits X 4 Serial interface: 2 channels AD converter: 10 bits X 8 channels Watchdog timer CS/WAIT controller
-- 64 K 64 K (OTP) -- 2K 64
50 ns 50 ns (20 MHz) 41.6 ns (24 MHz) QFP160 20 to 70
TMP94PS40AF DRAM controller: 2 channels TMP94C251F TMP94CS50F
24 MHz operation
DA converter: 8 bits X 2 channels
50 ns 64 K
QFP144
5 : Sample under shipment : Under development : Planned
900 Series: Seamless High-Performance Upgrade
Package and ROM product lines provide a timely response to customer needs
900/H2 Product Road Map
ility atibers p om roll e c rocont eries cod mic 0S tion eries of 90 uc S str 900- that ll in16-bit e 4X Fu ith anc w orm f Per
20 MHz
Processing capability improved by a factor of 4
· Code compatibility · 32-bit speed
High speed/embedded flash memory/high-capacity ROM
24 MHz
64-KB internal ROM
TMP94CS40A TMP94PS40A
Processing capability
TMP94C241A
Number of pins: 144
TMP94CS50 TMP94C251
: Under development : Planned
900 / H
2
TMP94CS40AF Block Diagram
PG0 to PG7 (AN0 to AN7) VREFH VREFL ADVCC ADVSS (TXD0) PF0 (RXD0) PF1 (SCLK0 / CTS0) PF2 (TXD1) PF4 (RXD1) PF5 (SCLK1 / CTS1) PF6 (TO7 / TO1) PC0
900 / H2 CPU
10 - BIT 8-CH A D CONVERTER
DVCC [8] DVSS [8]
SERIAL I / O (CH 0) SERIAL I / O (CH 1)
XWA XBC XDE XHL XIX XIY XIZ XSP
W B D H IX IY IZ SP 32 bits SR PC
A C E L
OSC
CLVCC CLVSS X1 X2 CLK AM0 to AM1 RESET TEST0 to TEST1
INTERRUPT CONTROLLER
NMI
F
WATCH DOG TIMER PORT 0 PORT 1 PORT 2 PORT 3
WDTOUT P00 to P07 (D0 to D7) P10 to P17 (D8 to D15) P20 to P27 (D16 to D23) P30 to P37 (D24 to D31) P40 to P47 (A0 to A7) P50 to P57 (A8 to A15) P60 to P67 (A16 to A23) P70 (RD) P71 (WRLL) P72 (WRLH) P73 (WRHL) P74 (WRHH) P75 (BUSRQ) P76 (BUSAK) PH0 (TC0) PH1 (TC1) PH2 (TC2) PH3 (TC3) PH4 (INT0)
8 -BIT TIMER (TIMER 0) 8 -BIT TIMER (TIMER 1)
(TOB / TO3) PC1
8 - BIT TIMER (TIMER 2) 8 - BIT TIMER (TIMER 3)
2-KB RAM
PORT 4 PORT 5 PORT 6
(TO4) PD0 (INT4 / TI4) PD1 (INT5 / TI5) PD2 (TO6) PD4 (INT6 / TI6) PD5 (INT7 / TI7) PD6 (TO8) PE0 (INT8 / TI8) PE1 (INT9 / TI9) PE2 (TOA) PE4 (INTA / TIA) PE5 (INTB / TIB) PE6 (LCAS0 / CAS0) PA0 (UCAS0) PA1 (OE0) PA2 (OE1) PA3 (WE0) PA4 (LLCAS1 / LCAS1 / CAS1) PB0 (LUCAS1 / UCAS1 ) PA1 (HLCAS1 ) PA2 (HUCAS1 ) PA3 (WE1) PA4
16 - BIT TIMER (TIMER 4)
16 - BIT TIMER (TIMER 6) PORT 7 16 - BIT TIMER (TIMER 8)
8 - BIT TIMER (TIMER A) PORT H
64-KB ROM
PORT Z DRAM CONTROLLER (2 channels) MEMORY CONTROLLER (6 channels)
PZ0 to PZ7 P80 (CS0) P81 (CS1/RAS0) P82 (CS2) P83 (CS3/RAS1) P84 (CS4) P85 (CS5) P86 (WAIT)
TMP94CS40AF Specifications
q Original high-speed 32-bit CPU core (900/H2 CPU)
s Full instruction code compatibility with TLCS-900, TLCS-900/L and TLCS-900/H Series s 16-MB linear address space s General-purpose registers and register banks s Internal data bus width: 32 bits s Micro DMA: 8 channels
q Memory controller
s Chip Select/WAIT/bus width control: 6 blocks
q DRAM controller: 2 channels
s Direct interface: 8/16/32-bit data bus s High-speed page mode supported
q Minimum instruction execution time: 50 ns (20 MHz) q Internal ROM: 64 KB (Internal PROM: 64 KB ) Internal RAM: 2 KB (32 bits, one clock cycle access) q External memory expansion
s Expandable to 16 MB (shared program/data) s External 8/16/32-bit data bus connectable simultaneously to 8-, 16- and 32-bit devices s External start-up data bus width select pin (8/16/32-bit bus selectable)
q q q q q q
8-bit timer: 4 channels 16-bit timer: 4 channels Serial interface: 2 channels 10-bit AD converter: 8 channels Watchdog timer Interrupt function Internal I/O: 18 External pins: 10 q 5 V/20 MHz (10 MHz input externally) q 160-pin mini-flat package
3
Maximizes Performance of a Wide Range of Memory Devices
The 900/H2 Series can be directly connected to a wide range of external memory devices without the need for external circuits. The internal memory is connected via a 32-bit data bus. Internal RAM can be accessed in one clock cycle.
900 /H2
Internal RAM (one clock cycle access) Internal ROM (interleaved access)
External memory
CPU core
SRAM
Mask ROM (suppor ts Page Mode)
DRAM (suppor ts Page Mode)
32-bit data bus
8/16/32-bit data bus
Improved DRAM Control Function
(a) 2 CAS method 16-bit width DRAM
Address Data
RAS UCAS LCAS RD WE
q Direct connection to a wide range of DRAM devices is possible. q Because the CPU and the memory refresh are asynchronous, access to non-DRAM memory devices does not degrade performance.
900 / H2
16-bit DRAM (2 CAS method)
(b) 2 WE method 16-bit width DRAM
Address Data
RAS CAS UW(HWR) LW(WR) RD
900 / H2
16-bit DRAM (2 WE method)
(c) 8-bit DRAM
Address Data
900 / H2
RAS CAS RD WE(WR)
8-bit DRAM
Enhanced High-Speed Data Transfer Function (micro DMA)
The 900/H2 Series incorporates high-speed data transfer -- as performed by a DMAC (direct memory access controller) -- as a standard function.
Function and Performance Comparison
Parameter
Number of channels Minimum transfer time
900, 900/L Series
4 channels 1600 ns/2 bytes Interrupt No memory, Memory
900/H, 900/L1 Series
4 channels 640 ns/2 bytes Interrupt and software trigger No I/O I/O memory, Memory I/O I/O
900/H2 Series
8 channels 250 ns/4 bytes Interrupt and software trigger Yes memory, Memory I/O, Memory memory
Start-up sources Burst Mode Transfer modes I/O
4
Support for Function Upgrades to Advanced Systems
Application example for printer
The following depicts a system for the efficient processing of data received via a high-speed communications interface; in this case, a system to print the output from multimedia equipment directly.
Address bus DVC
TMP94CS40A
Flash memory
(supports wide range of flash memory devices)
DRAM
data buffer Head image buffer
MROM characters
I/F block ASIC
DRAMC
IEEE1284 IEEE1394 PC 8-channel micro DMA
Carriage detection
Data bus
Digital still camera Serial interface
64-KB ROM
Image processing engine ASIC Paper feed stepping motor driver Carriage stepping motor driver
Printer head Motor driver Head driver
RS232C
900/H2
CPU core Control switch LED Paper sensor
Substantially improved data processing functions
· 900/H2 : High-speed CPU Internal/external bus parallel processing · Micro DMA : 8 channels based on hardware DMA · DRAMC : Directly connectable to a wide range of DRAM devices · ROM : Only core program resident
Designed to Allow Smooth Migration to the TX Series
The numerous peripheral I/O devices that have been proven to work with the 900 Family are also compatible with the TX System RISC family. Toshiba's solutions for more advanced system performance make effective use of existing resources.
Toshiba Microcontroller Road Map
[MIPS]
· 32-bit RISC · MIPS 16 added (high code efficiency) · Ultra-low power dissipation · Code compatibility · Upgraded to 32-bit processing (processing capability increased by a factor of 4)
TX19
Peripheral I/O device compatibility
RISC core CISC core
900 / H2
· 32-bit CISC · 24-MHz operation · Separate internal and external buses
10 · Processing capability increased by a factor of 2
900 / H
900 / L1
· Low voltage · Power dissipation reduced by 75% · Low noise
900
1
900 / L
· Low voltage · Power consumption halved
5
900-Series CPU Core Enhances Performance of Advanced Embedded Systems
Conditions required for embedded application IP 1. Compact core
q Custom instructions written specially for embedded applications, optimized circuit structure q Totally original architecture designed for efficient use of C language code Substantial improvement in C language code generation efficiency (code size can be as small as 1.2× equivalent assembly code) Significant improvement in program efficiency (especially for programs larger than 64 KB)
2. Real-time response
q Multi-bank system Substantial improvement in interrupt response speed allows system to operate at maximum efficiency. Amount of program code can also be reduced. q High-speed data transfer function (micro DMA) Supports high-speed data transfer (equivalent to hardware DMA) as a standard function. 900/H2 core has eight channels.
3. Line of products supporting advanced user systems
q Seamless core product line 16-bit core family and 32-bit core 900/H2 offer full instruction code compatibility. C o m m o n development environment for 16/32-bit systems enables development system to respond swiftly to market changes. q Fully developed memory support DRAMC can respond flexibly to system demands and memory market trends.
CPU Core Performance
Instruction · Data transfer 1 LD reg, reg 50 · Data transfer 2 LD reg, mem 100 · Arithmetic operation ADD reg, imm · Bit processing SET imm, reg · Jump JR disp8 6 400 100 240 50 50 240 240 50 50 320 50 480 320 100 320 100 480
Current products 160 50 900/H2 series Current products 160 50 900/H2 series Current products 160 900/H2 series
Unit: ns 32 bits
8 bits
Operand Size 16 bits
Others parts begin by 90
90-1
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