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Details, datasheet, quote on part number:JT6N57
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Datasheet text preview:
JT6N57
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
JT6N57
LSIs for Serial Port Controller with Built-in Non-Volatile Memory
JT6N57 is a low-power-dissipation, low-operating-voltage LSI developed using Toshiba's CMOS and EEPROM technology combined. The LSI integrates a serial I/O controller and 4-KB EEPROM on a single chip. With low power dissipation, 3- to 5-V operating voltage, Sleep mode, and battery level detector, JT6N57 is ideal for hand-held devices and battery-operated systems. To protect data, JT6N57 can prohibit write to EEPROM when the LSI is abnormal (eg, power supply voltage is low). JT6N57 features protect bits which prevent written data from being erroneously overwritten, a response function which confirms that operation is normal, and a parity check function which confirms that data communications are performed correctly.
Features
· · · · · · · · · · · Built-in EEPROM: 4 Kbytes (32 bytes/page × 128 pages) Pins: five (VDD, GND, CLK, RST , I/O (I/O-port-only pin)) Battery level detector (anti-erroneous EEPROM write operations) Byte/Page-write/read function Sleep mode (low-power dissipation at standby for input) Operating voltage: 2.7 to 5.5 V Operating frequency: 1 kHz to 1 MHz (1 kHz to 100 kHz for Page-write) Response function and function to display after reset information about the LSI type EEPROM protect bits against erroneous overwrite Parity check function Package: chip/wafer Note: Overwrite time: 8 ms (max) 5 Number of writes: 10 times (provisional) Year for retaining data: 10 years (provisional)
000707EAA1
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice.
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JT6N57
Block Diagram
JT6N57
I/O
Serial I/O control
RST
System control
EEPROM (4 Kbytes)
CLK V DD GND
Pad Functions
Pad I/O
RST
Input or Output Input or output Input Input
Name and Function I/O port: Serial interface for external devices. Internally pulled up. Reset: Input for reset signals from external devices. Schmitt trigger input with internal pull-up. Clock: Input for clock signals from external devices. Schmitt trigger input with internal pull-up. Power supply: Input for power supply from external devices. Ground: Input for power supply from external devices. (+0 V)
CLK V DD GND
Equivalent Circuit Diagrams
(1) CLK, RST Both CLK and RST are Schmitt trigger inputs with a pull-up resistor.
Input
CLK or RST
Figure 1
(2) I/O Serial I/O interface with a pull-up resistor.
I/O control Output Input Latch I/O
Figure 2
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JT6N57
External View
GND Y X (0, 0)
V DD
RST
Chip size LX: 2.19 mm LY: 2.88 mm Pad size 100 µm × 100 µm
I/O
CLK
Pad Coordinates
Signal
RST
(µm, µm) (X Point, Y Point) (900, 1060) (-880, 1050)
(X Point, Y Point) (900, -50) (900, -1030) (-880, -1040)
Signal V DD GND
CLK I/O
1. Data Memory
Features are listed below: · 4 Kbytes (32 bytes × 128 pages) · Automatic byte overwrite · Automatic page overwrite (32 bytes) · Data protection function by protect bits · Write cycle time: 8 ms (max) Figure 3 below is the memory map.
Pages (A11~A5) 0000 0020
Addresses within page (A4 to A0) 0001 0021 .... .... 32 bytes ~ ~ .... .... 001E 003E 001F 003F
(1 bit/page) Protect bit (D7)
128 pages
0FC0 0FE0
0FC1 0FE1
.... ....
~ ~
.... ....
0FDE 0FFE
0FDF 0FFF
Figure 3
Memory Map
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