Details, datasheet, quote on part number: TC59SM716AFT
PartTC59SM716AFT
CategoryMemory => DRAM
DescriptionType = Sdram ;; Density (Mb) = 128 ;; Geometry = 32M X 4 ;; Refresh = 4K/64ms ;; Features = PC100/PC133 ;; Power = Standard/low ;; Date = 2000-02-08
CompanyToshiba America Electronic Components, Inc.
DatasheetDownload TC59SM716AFT datasheet
  

 

Features, Applications
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

4 BANKS 16-BITS SYNCHRONOUS DYNAMIC RAM 4 BANKS 8-BITS SYNCHRONOUS DYNAMIC RAM 4 BANKS 4-BITS SYNCHRONOUS DYNAMIC RAM DESCRIPTION

is a CMOS synchronous dynamic random access memory organized 4 banks 16 bits and TC59SM708AFT/AFTL is organized as 4,194,304 words 4 banks 8 bits and TC59SM704AFT/AFTL is organized as 8,388,608 words 4 banks 4 bits. Fully synchronous operations are referenced to the positive edges of clock input and can transfer data to 143M words per second. These devices are controlled by commands setting. Each bank are kept active so that DRAM core sense amplifiers can be used as a cache. The refresh functions, either Auto Refresh or Self Refresh are easy to use. By having a programmable Mode Register, the system can choose the most suitable modes which will maximize its performance. These devices are ideal for main memory in applications such as work-stations.

FEATURES

tRAS Active to Precharge Command Period (min) tAC tRC Access Time from CLK (max) Ref/Active to Ref/Active Command Period (min)

ICC1 Operation Current (max) (Single bank) ICC4 Burst Operation Current (max) ICC6 Self-Refresh Current (max)

Single power supply to 143 MHz clock frequency Synchronous operations: All signals referenced to the positive edges of clock Architecture: Pipeline Organization TC59SM716AFT/AFTL: 2,097,152 words 4 banks 16 bits TC59SM708AFT/AFTL: 4,194,304 words 4 banks 8 bits TC59SM704AFT/AFTL: 8,388,608 words 4 banks 4 bits Programmable Mode register Auto Refresh and Self Refresh Burst Length: Full page CAS Latency: 2, 3 Single Write Mode Burst Stop Function Byte Data Controlled by L-DQM, U-DQM (TC59SM716) 4K Refresh cycles/64 ms Interface: LVTTL Package TC59SM704AFT/AFTL: TSOPII54-P-400-0.80B

TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice.

Address Bank Select TC59SM708AFT/AFTL TC59SM704AFT/AFTL VCC DQ0 NC VCCQ DQ1 DQ0 VSSQ DQ2 NC VCCQ DQ3 DQ1 VSSQ DQ7 NC VCC LDQM NC WE CAS RAS A2 A3 VCC VSS NC VSSQ NC DQ3 VCCQ NC VSSQ NC DQ2 VCCQ NC VSS NC DQM CLK CKE A5 A4 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE A5 A4 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC UDQM CLK CKE A5 A4 VSS

Chip Select Row Address Strobe Column Address Strobe Write Enable

Output Disable/Write Mask UDQM/LDQM (TC59SM716) CLK CKE VCC VSS VCCQ VSSQ NC Clock inputs Clock enable Power (+3.3 V) Ground Power (+3.3 V) (for DQ buffer) Ground (for DQ buffer) No Connection

CONTROL SIGNAL GENERATOR COLUMN DECODER ROW DECODER ROW DECODER COLUMN DECODER
A10 MODE ADDRESS BUFFER BS0 BS1 REFRESH COUNTER COLUMN COUNTER REGISTER

NOTE: The TC59SM704AFT/AFTL configuration is of cell array with the DQ pins numbered DQ0~DQ3. The TC59SM708AFT/AFTL configuration is of cell array with the DQ pins numbered DQ0~DQ7. The TC59SM716AFT/AFTL configuration is of cell array with the DQ pins numbered DQ0~DQ15.


 

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