Details, datasheet, quote on part number: TC59SM816CMB
PartTC59SM816CMB
CategoryMemory => DRAM
DescriptionType = Sdram ;; Density (Mb) = 256 ;; Geometry = 64M X 4 ;; Refresh = 8K/64ms ;; Features = PC100/PC133; 60-CSP ;; Power = Standard/low ;; Date = 2001-08-08
CompanyToshiba America Electronic Components, Inc.
DatasheetDownload TC59SM816CMB datasheet
  

 

Features, Applications
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

4 BANKS 16-BITS SYNCHRONOUS DYNAMIC RAM 4 BANKS 8-BITS SYNCHRONOUS DYNAMIC RAM 4 BANKS 4-BITS SYNCHRONOUS DYNAMIC RAM DESCRIPTION

is a CMOS synchronous dynamic random access memory organized 4 banks 16 bits and TC59SM808CMB/CMBL is organized as 8,388,608 words 4 banks 8 bits and The TC59SM804CMB/CMBL is organized as 16,777,216 words 4 banks 4 bits. Fully synchronous operations are referenced to the positive edges of clock input and can transfer data to 143M words per second. These devices are controlled by commands setting. Each bank are kept active so that DRAM core sense amplifiers can be used as a cache. The refresh functions, either Auto Refresh or Self Refresh are easy to use. By having a programmable Mode Register, the system can choose the most suitable modes which will maximize its performance. These devices are ideal for main memory in applications such as work-stations.

FEATURES

tRAS Active to Precharge Command Period (min) tAC tRC Access Time from CLK (max) Ref/Active to Ref/Active Command Period (min)

ICC1 Operation Current (max) (Single bank) ICC4 Burst Operation Current (max) ICC6 Self-Refresh Current (max)

Single power supply to 143 MHz clock frequency Synchronous operations: All signals referenced to the positive edges of clock Architecture: Pipeline Organization TC59SM816CMB/CMBL: 4,194,304 words 4 banks 16 bits TC59SM808CMB/CMBL: 8,388,608 words 4 banks 8 bits TC59SM804CMB/CMBL: 16,777,216 words 4 banks 4 bits Programmable Mode register Auto Refresh and Self Refresh Burst Length: Full page CAS Latency: 2, 3 Single Write Mode Burst Stop Function Byte Data Controlled by LDQM, UDQM (TC59SM816) 8K Refresh cycles/64 ms Interface: LVTTL Package TC59SM804CMB/CMBL: P-TFBGA60-0816-0.80AZ

TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk.

Chip Select Row Address Strobe Column Address Strobe Write Enable

Clock input Clock enable Power (+3.3 V) Ground Power (+3.3 V) (for DQ buffer) Ground (for DQ buffer) No Connection

TC59SM804CMB/CMBL 1 VSS DQ8 NC CKE A8 A6 VSS 2 DQ15 VSSQ VDDQ DQ11 VSSQ VDDQ NC VSS UDQM CLK A4 1 VSS DQ4 NC CKE A8 A6 VSS 2 DQ7 VSSQ VDDQ DQ5 VSSQ VDDQ NC VSS DQM CLK A4 1 VSS DQ2 NC CKE A8 A6 VSS 2 NC VSSQ VDDQ NC VSSQ VDDQ NC VSS DQM CLK A4 NC VDDQ VSSQ NC VDDQ VSSQ NC VDD NC RAS A3 6 VDD 5 DQ0 VDDQ VSSQ DQ2 VDDQ VSSQ NC VDD NC RAS A3 6 VDD 5 DQ0 VDDQ VSSQ DQ4 VDDQ VSSQ NC VDD LDQM RAS A3 6 VDD DQ7 NC

The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice.

CONTROL SIGNAL GENERATOR COLUMN DECODER ROW DECODER ROW DECODER COLUMN DECODER
A10 MODE ADDRESS BUFFER BS0 BS1 REFRESH COUNTER COLUMN COUNTER REGISTER

NOTE: The TC59SM804CMB/CMBL configuration is of cell array with the DQ pins numbered DQ0~DQ3. The TC59SM808CMB/CMBL configuration is of cell array with the DQ pins numbered DQ0~DQ7. The TC59SM816CMB/CMBL configuration is of cell array with the DQ pins numbered DQ0~DQ15.


 

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