Details, datasheet, quote on part number: TC59WM803BFT
PartTC59WM803BFT
CategoryMemory => DRAM
DescriptionType = DDR ;; Density (Mb) = 256 ;; Geometry = 64M X 4 ;; Refresh = 8K/64ms ;; Features = DDR266A, DDR266B, DDR200 ;; Power = Standard ;; Date = 2000-12-13
CompanyToshiba America Electronic Components, Inc.
DatasheetDownload TC59WM803BFT datasheet
  

 

Features, Applications
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

× 4 BANKS × 16-BITS SYNCHRONOUS DYNAMIC RAM × 4 BANKS × 8-BITS SYNCHRONOUS DYNAMIC RAM × 4 BANKS × 4-BITS SYNCHRONOUS DYNAMIC RAM DESCRIPTION

is a CMOS Double Data Rate synchronous dynamic random access memory organized as 4,194,304 words × 4 banks × 16 bits and TC59WM807BFT is organized as 8,388,608 words × 4 banks × 8 bits and the TC59WM803BFT is organized as 16,777,216 words × 4 banks × 4 bits. All inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. And Write and Read data are synchronized with both edges of DQS (Data Strobe). These devices are ideal for main memory applications such as work-stations.

FEATURES
tRAS Active to Precharge Command Period (min) tRC Active to Ref/Active Command Period (min)

IDD1 Operation Current (max) (Single bank) lDD4 Burst Operation Current (max) lDD6 Self-Refresh Current (max)

Fully Synchronous Operation Double Data Rate (DDR) Data Input/Output and DM are synchronized with both edges of DQS (Write/Read Data Strobe). Differential Clock inputs All input signals reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. Fast cycle time 7 ns minimum Clock: 143 MHz maximum Data: 286 Mbps/pin maximum Auto Refresh and Self Refresh Precharged Power Down and Active Power Down Write Data Mask Write Latency = 1 Organization: x4 8K row × 2K col. × 4 banks × 4 bits x8 8K row × 1K col. × 4 banks × 8 bits x16 8K row × 512 col. × 4 banks × 16 bits Output Strobe Signal: Bidirectional Programmable CAS Latency and Burst Length: CAS Latency 2, 2.5 Burst Length Interface: SSTL-2 Package: × 875 mil, 66 pin TSOP II, 0.65 mm Pin pitch (TSOPII66-P-400-0.65)

TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk.

Address Bank Address TC59WM807BFT TC59WM815BFT VDD NC2 DQ0 VDDQ DQ0 DQ1 VSSQ NC DQ2 VDDQ DQ1 DQ3 VSSQ NC1 NC VSSQ VDDQ NC2 LDQS NC1 VDD 2 NC LDM WE CAS RAS A2 A3 VDD VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC1 VSSQ UDQS NC1 VREF VSS UDM CLK CKE A5 A4 VSS DQ7 VSSQ NC2 DQ6 VDDQ NC2 DQ5 VSSQ NC2 DQ4 VDDQ NC2 NC1 VSSQ DQS NC1 VREF VSS DM CLK CKE A5 A4 VSS NC2 VSSQ NC2 DQ3 VDDQ NC2 VSSQ NC2 DQ2 VDDQ NC2 NC1 VSSQ DQS NC1 VREF VSS DM CLK CKE A5 A4 VSS

Chip Select Row Address Strobe Column Address Strobe Write Enable

Write Mask UDM/LDM (x16) CLK, (/CLK) DQS (x4/x8) Write/Read Data Strobe U/LDQS (x16) CKE VDD VSS VDDQ VSSQ VREF , NC

Clock Enable Power (+2.5 V) Ground Power (+2.5 V) (for I/O buffer) Ground (for I/O buffer) Reference Voltage Not Connected

The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice.

CONTROL SIGNAL GENERATOR COLUMN DECODER ROW DECODER ROW DECODER COLUMN DECODER
A10 MODE ADDRESS BUFFER BS0 BS1 REFRESH COUNTER COLUMN COUNTER REGISTER

Note: The TC59WM803BFT configuration is of cell array with the DQ pins numbered DQ~DQ3. The TC59WM807BFT configuration is of cell array with the DQ pins numbered DQ0~DQ7. The TC59WM815BFT configuration is of cell array with the DQ pins numbered DQ0~DQ15.


 

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