FEATURES Extended Power Supply Voltage Single Vcc for Read and Programming (Vcc to 5.5 V)· Low Power (Isb @ 5.5 V)· I²C Bus, 2-Wire Serial Interface· Support Byte Write and Page Write (16 Bytes)· Automatic Page write Operation (maximum 10 ms) Internal Control Timer Internal Data Latches for 16 Bytes· Hardware Data Protection by Write Protect Pin· High Reliability CMOS Technology with EEPROM Cell Endurance : 1,000,000 Cycles Data Retention : 100 Years DESCRIPTION: The Turbo is a serial 16K EEPROM fabricated with Turbo's proprietary, high reliability, high performance CMOS technology. It's 16K of memory is organized x 8 bits. The memory is configured as 128 pages with each page containing 16 bytes. This device offers significant advantages in low power and low voltage applications. The Turbo IC 24C16 uses the I²C addressing protocol and 2-wire serial interface which includes a bidirectional serial data bus synchronized by a clock. It offers a flexible byte write and a faster 16-byte page write. The data in the upper half of memory can be protected by a write protect pin. The Turbo 24C16 is assembled in either a 8-pin PDIP or 8-pin SOIC package. Pin #1, #2, and #3 are not connected (NC). Pin #4 is the ground (Vss). Pin #5 is the serial data (SDA) pin used for bidirectional transfer of data. Pin #6 is the serial clock (SCL) input pin. Pin #7 is the write protect (WP) input pin, and Pin #8 is the power supply (Vcc) pin. All data is serially transmitted in bytes (8 bits) on the SDA bus. To access the Turbo IC 24C16 (slave) for a read or write operation, the controller (master) issues a start condition by pulling SDA from high to low while SCL is high. The VCC master then issues the device address byte which consists (B9) (B8) (R/W). The most significant bits WP (1010) are a device type code signifying an EEPROM deSCL vice. The B[10:8] bits are the 3 most significant bits of the SDA memory address. The read/write bit determines whether do a read or write operation. After each byte is transmitted, the receiver has to provide an acknowledge by pulling the SDA bus low on the ninth clock cycle. The acknowledge is a handshake signal to the transmitter indicating a successful data transmission.
PIN DESCRIPTION WRITE PROTECT (WP) When the write protect input is connected to Vcc, the upper half of memory (400-7FFH) is protected against write operations. For normal write operation, the write protect pin should be grounded. When this pin is left unconnected, WP is interpreted as zero. SERIAL DATA (SDA) SDA is a bidirectional pin used to transfer data in and out of the Turbo IC 24C16. The pin is an open-drain output. A pullup resistor must be connected from SDA to Vcc. SERIAL CLOCK (SCL) The SCL input synchronizes the data on the SDA bus. It is used in conjunction with SDA to define the start and stop conditions. It is also used in conjunction with SDA to transfer data to and from the Turbo IC 24C16.
DESCRIPTION (Continued): For a write operation, the master issues a start condition, a device address byte, a memory address byte, and then to 16 data bytes. The Turbo IC 24C16 acknowledges after each byte transmission. To terminate the transmission, the master issues a stop condition by pulling SDA from low to high while SCL is high.
For a read operation, the master issues a start condition and a device address byte. The Turbo IC 24C16 acknowledges, and then transmits a data byte, which is accessed from the EEPROM memory. The master acknowledges, indicating that it requires more data bytes. The Turbo IC 24C16 transmits more data bytes, with the memory address counter automatically incrementing for each data byte, until the master does not acknowledge, indicating that it is terminating the transmission. The master then issues a stop condition.
DEVICE OPERATION: BIDIRECTIONAL BUS PROTOCOL: The Turbo IC 24C16 follows the I²C bus protocol. The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving device as a receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates the data transfers, and provides the clock for both transmit and receive operations. The Turbo IC 24C16 acts as a slave device in all applications. Either the master or the slave can take control of the SDA bus, depending on the requirement of the protocol. START/STOP CONDITION AND DATA TRANSITIONS: While SCL clock is high, a high to low transition on the SDA bus is recognized as a START condition which precedes any read or write operation. While SCL clock is high, a low to high transition on the SDA bus is recognized as a STOP condition which terminates the communication and places the Turbo IC 24C16 into standby mode. All other data transitions on the SDA bus must occur while SCL clock is low to ensure proper operation. ACKNOWLEDGE: All data is serially transmitted in bytes (8 bits) on the SDA bus. The acknowledge protocol is used as a handshake signal to indicate successful transmission of a byte of data. The bus transmitter, either the master or the slave (Turbo IC 24C16), releases the bus after sending a byte of data on the SDA bus. The receiver pulls the SDA bus low during the ninth clock cycle to acknowledge the successful transmission of a byte of data. If the SDA is not pulled low during the ninth clock cycle, the Turbo IC 24C16 terminates the data transmission and goes into standby mode. For the write operation, the Turbo IC 24C16 acknowledges after the device address byte, acknowledges after the memory address byte, and acknowledges after each subsequent data byte. For the read operation, the Turbo IC 24C16 acknowledges after the device address byte. Then the Turbo IC 24C16 transmits each subsequent data byte, and the master acknowledges after each data byte transfer, indicating that it requires more data bytes. The Turbo IC 24C16 monitors the SDA bus for the acknowledge. To terminate the transmission, the master does not acknowledge, and then sends a stop condition.
Note: The write cycle time tWC is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.
DATA STABLE DATA STABLE DATA CHANGE