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Part: 28C64AM-1
Category:
Memory
Description:
Company: Turbo IC, Inc.
Datasheet: Download 28C64AM-1 datasheet File size : 99 kB
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Turbo IC, Inc.
28C64A
HIGH SPEED CMOS 64K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 8K X 8 BIT EEPROM
FEATURES: · 120 ns Access Time · Automatic Page Write Operation Internal Control Timer Internal Data and Address Latches for 64 Bytes · Fast Write Cycle Times Byte or Page Write Cycles: 10 ms Time to Rewrite Complete Memory: 1.25 sec Typical Byte Write Cycle Time: 160 µsec · Software Data Protection · Low Power Dissipation 50 mA Active Current 200 µA CMOS Standby Current · Direct Microprocessor End of Write Detection Data Polling · High Reliability CMOS Technology with Self Redundant EEPROM Cell Endurance: 100,000 Cycles Data Retention: 10 Years · TTL and CMOS Compatible Inputs and Outputs · Single 5 V ± 10% Power Supply for Read and Programming l Operations · JEDEC Approved Byte-Write Pinout
A7 NC A12 A6 A5 A4 A3 A2 A1 A0 NC I/O0 VCC NC WE A8 A9 A11 NC OE A10 CE I/O7 I/O6 NC NC A12 5 4 3 2 1 32 31 3029 6 28 7 8 9 10 11 27 26 25 24 23 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O1 GND I/O3 I/O2 NC I/O5 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
DESCRIPTION: The Turbo IC 28C64A is a 8K X 8 EEPROM fabricated with Turbo's proprietary, high reliability, high performance CMOS technology. The 64K bits of memory are organized as 8K by 8 bits. The device offers access time of 120 ns with power dissipation below 250 mW. The 28C64A has a 64-bytes page write operation enabling the entire memory to be typically written in less than 1.25 seconds. During a write cycle, the address and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other microprocessor operations. The programming process is automatically controlled by the device using an inter nal control timer. Data polling on one or all I/O can be used to detect the end of a programming cycle. In addition, the 28C64A includes an user-optional software data write mode offering additional protection against unwanted (false) write. The device utilizes an error protected self redundant cell for extended data retention and endurance.
A11 A8 WE NC A7 A5 A3
OE A9 NC VCC A12 A6 A4
2 4 6 8 10 12 14
1 3 5 7 9 11 13
28 27 26 25 24 23 22 21 20 19 18 17 16 15
A10 I/O7 I/O5 I/O3 I/O2 I/O0 A1
CE I/O6 I/O4 GND I/O1 A0 A2
22 12 21 13 14 15 16 17 18 19 20
28 pins TSOP
I/O4
32 pins PLCC
28 pins PDIP
28 pins SOIC (SOG)
PIN DESCRIPTION
ADDRESSES (A0 - A12) The Addresses are used to select an 8 bits memor y location during a write or read operation. OUTPUT ENABLE (OE) The Output Enable input activates the output buffers during the read operations. CHIP ENABLES (CE) The Chip Enable input must be low to enable all read/write operation on the device. By setting CE high, the device is disabled and the power consumption is extremely low with the standby current below 200 µA. WRITE ENABLE (WE) The Write Enable input initiates the writing of data into the memory. DATA INPUT/OUTPUT (I/O0-I/O7) Data Input/Output pins are used to read data out of the memory or to write Data into the memory.
Turbo IC, Inc.
28C64A
DEVICE OPERATION
READ: The 28C64A is accessed like a static RAM. Read operations are initiated by both CE and OE going low and terminated by either CE or OE returning high. The outputs are at the high impedance state whenever CE or OE returns high. The two line control architecture gives designers flexibility in preventing bus contention. WRITE: A write cycle is initiated when CE and WE are low and OE is high. The address is latched internally on the falling edge of CE or WE whichever occurs last. The data is latched by the rising edge of CE or WE whichever occurs first. Once a byte write cycle has been started, the internal timer automatically generates the write sequence to the completion of the write operation. PAGE WRITE OPERATION: The page write operation of 28C64A allows one to 64 bytes of data to be serially loaded into the device and then simultaneously written into memory during the internally generated write cycle. After the first byte has been loaded, successive bytes of data may be loaded until the full page of 64 bytes is loaded. Each new byte to be written must be loaded within 200 µs of the previously loaded byte. The page address defined by the addresses A6-A12 is latched by the first CE or WE falling edge which initiates a writing cycle and they will stay latched until the completion of the page write. Any changes in the page addresses during the load-write cycle will not affect the initially latched page addresses. Addresses A0 A5 are used to define which bytes will be loaded and written within the 64 bytes page. The bytes may be loaded in any order that is convenient to the user. The content of a loaded byte may be altered at any time during the loading cycle if the maximum allowed byte-load time (200 µs) is not exceeded. Only loaded bytes within the page will be written; no rewriting will occur to the non-selected bytes in the page. DATA POLLING: The 28C64A features DATA POLLING to indicate the completion of a write cycle to the host system. During a byte or page write cycle, an attempted read of the last byte loaded into the page will result in the complement of the loaded byte on all outputs I/O0 - I/O7 (i.e. loaded data 01010110, read data 10101001). Data Polling feature may be used by an attempted read on one or more outputs (whatever is convenient for the system developer). Once the write cycle has been completed, true data is valid on all outputs and the next cycle may be started. DATA PROTECTION: The 28C64A has three hardware features to protect the written content of the memory against inadvertent writes : a.) Vcc threshold detector: If Vcc is below 2.5 V, the write capabilities of the chip is inhibited for whatever input conditions. b.) Noise protection: A WE, OE, or CE pulse less than 10 ns in width is not able to initiate a write cycle. c.) Write inhibit: Holding OE at low, or CE at high, or WE at high inhibits the write cycle. SOFTWARE WRITE PROTECTION: The 28C64A offers a software controlled data write protection feature. The device is delivered to the user with the software data write protection DISABLED; i.e. the device will go to the data write operation as long as Vcc exceeds 2.5 V and CE, WE, and OE inputs are set at write mode levels. The 28C64A can be automatically protected against an accidental write operation during power-up or power-down without any external circuitry by enabling the software data write protection features. This features is enabled after the first write cycle which includes the software algorithm. After this operation is done, the data write function of the device may be perfor med only if every page write cycle is preceded by the software algorithm. The device will maintain its software protect feature for the rest of its life unless that the software algorithm for disabling the protection is implemented. SOFTWARE ALGORITHM: The 28C64A has an internal register for the software algorithm which enables the memory to provide the user with additional features: a.) Software Write Protect Enable A sequence of three dummy data writes to the memory will activate internal EEPROM fuses during the first page write cycle. These EEPROM fuses will reject any write attempts of new pages of data unless the three dummy data writes are repeated at the beginning of any page writes. The timing for the dummy data and addresses must be the same as for a normal write operation. A violation of the three steps write protect sequence in data or address timing and content will abort the procedure and reset the device to the starting point condition. Note: After the three dummy data writes, at least one page load/ write cycle must be performed. If no additional page data is added to the three dummy data writes, the software write protect will not be enabled until the next write, which will not be protected. Table 1 shows the required procedure for enabling the software write protect: Step 1 2 3 4-67 Mode Page Write Page Write Page Write Page Write Address A12-A0 1555 Hex 0AAA Hex 1555 Hex Address Data I/O 7-0 AA Hex 55 Hex A0 Hex Data
b.) Software Write Protect Disable The software algorithm of 28C64A includes a six steps sequence of dummy data writing to disable the software write protect feature described in a.). The six steps write sequence shown in Table 2 must be performed at the beginning of a page write cycle. A violation of the six steps write sequence in data or address timing and content will abort the procedure and reset the chip to the starting point condition. After a page write cycle including the six steps write sequence has been performed, the 28C64A does not require the use of three dummy data writes described in a.) for the following page write cycle. The device is at the software write protect disabled state. Note: After the six dummy data writes, at least one page load/ write cycle must be performed. If no additional page data is added to the six dummy data writes, the software write protect disable will not be activated. Table 2 shows the required procedure for disabling the software write protect: step 1 2 3 4 5 6 7-70 Mode Page Write Page Write Page Write Page Write Page Write Page Write Page Write Address A12-A0 1555 Hex 0AAA Hex 1555 Hex 1555 Hex 0AAA Hex 1555 Hex Address Data I/O 7-0 AA Hex 55 Hex 80 Hex AA Hex 55 Hex 20 Hex Data
c.) Software Chip Clear The software algorithm of 28C64A includes a sequence of six steps dummy data writing to perform a chip clear operation. Table 3 shows the six steps write sequence to perform the software chip clear operation: Step 1 2 3 4 5 6 Mode Page Write Page Write Page Write Page Write Page Write Page Write Address A12-A0 1555 Hex 0AAA Hex 1555 Hex 1555 Hex 0AAA Hex 1555 Hex Data I/O 7-0 AA Hex 55 Hex 80 Hex AA Hex 55 Hex 10 Hex
At the end of the six steps write sequence shown in Table 3, the device automatically activates its internal timer to control the chip
Turbo IC, Inc.
28C64A
erase cycle; typically takes 20 msec. After a software chip clear operation has been completed, all 64K bit locations of memory show high level at read operation mode. d.) Software Autoclear Disable Mode This software algorithm disables the internal automatic clear before write cycle. Table 4 shows the six steps needed to perform the autoclear disable mode: Step 1 2 3 4 5 6 7-70 Mode Page Write Page Write Page Write Page Write Page Write Page Write Page Write Address A12-A0 1555 Hex 0AAA Hex 1555 Hex 1555 Hex 0AAA Hex 1555 Hex Address Data I/O 7-0 AA Hex 55 Hex 80 Hex AA Hex 55 Hex 40 Hex Data ABSOLUTE MAXIMUM STRESS RANGES *
TEMPERATURE Storage: -65° C to 150° C Under Bias: -55° C to 125° C ALL INPUT OR OUTPUT VOLTAGES with respect to Vss +6 V to -0.3 V "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature Range: Commercial: Industr ial: Militar y: Vcc Supply Voltage: Endurance: Data Retention: 5 V ± 10% 100,000 Cycles/Byte (Typical) 10 Years 0° C to 70° C -40° C to 85° C -55° C to 125° C
Page write operation using the software autoclear disable mode will reduce programming time to typically 5 msec. The page write using software autoclear disable mode is usually used after a chip clear or a software chip clear operation. At the end of the six steps sequence, the autoclear before write is disabled and will stay that way unless a power-down occurs or the software autoclear enable procedure is initiated. e.) Software Autoclear Enable Mode Automatic page clear before page write can be restored to 28C64A either by Vcc power-down or by software autoclear enable mode. Table 5 shows the six steps page write procedure needed to enable software autoclear mode: Step 1 2 3 4 5 6 7-70 Mode Page Write Page Write Page Write Page Write Page Write Page Write Page Write Address A12-A0 1555 Hex 0AAA Hex 1555 Hex 1555 Hex 0AAA Hex 1555 Hex Address
(C) = (I) = (M) =
A.C. CHARACTERISTICS - READ OPERATION
28C64A-1 28C64A-2 28C64A-3 28C64A-4
Symbol tacc tce toe tdf toh
Data I/O 7-0 AA Hex 55 Hex 80 Hex AA Hex 55 Hex 50 Hex Data
COMMERICAL INDUSTRIAL MILITARY
Parameters Min M a x Min M a x Min Address to 120 150 Output Delay CE to Output 120 150 Delay OE to Output 70 90 OE to Output 0 40 0 60 0 In High Z Output Hold 0 0 0 from Address Changes, Chip Enable or Output Enable Whichever Occurs First
Max Min MaxUnit 200 250 ns 200 110 90 250 ns 150 ns 90 ns ns
0 0
D.C. CHARACTERISTICS Symbol Parameter Condition Icc Active Vcc Current
Min
Max 50 70 90 200 300
Units (C) (I) (M) (C) (I&M) mA mA mA µA µA mA
A.C. TEST CONDITIONS Output Load : 1 TTL Load and Cl=100 pF Input Rise and Fall Times : < 10 ns Input Pulse Level : 0 V to 3 V Timing Measurement Reference Level : 1.5 V
Isb1
Isb2
Iil
Iol
Vil Vih Vol Voh
CMOS Standby Current TTL Standby CE=Vih, OE=Vil, 3 Current All I/O Open, Other Inputs=Vcc Max Vin=Vcc Max Input 1 Leakage Current Output 10 Leakage Current Input Low -0.1 -0.8 Voltage Input High 2 Vcc+0.3 Voltage Output Low Iol=2.1 mA 0.45 Voltage Output High Ioh=-0.45 mA 2.4 Voltage
CE=OE=Vil; All I/O Open, Min Read or Write Cycle Time CE=Vcc-0.3 V to Vcc+1 V
A.C. Read Wave Forms
ADDRESS
ADDRESS VALID tacc tce tdf
µA
CE
µA
toe OE toh
V V V V
OUTPUT HIGH-Z OUTPUT VALID HIGH-Z
Turbo IC, Inc.
28C64A
A.C. WRITE CHARACTERISTICS Symbol tas tah tcs tch tcw twp toes toeh tds tdh tblc tlp twc twc Parameter Min Address Set-up Time 20 Address Hold Time 100 Write Set-up Time 0 Write Hold Time 0 CE Pulse Width 150 WE Pulse Width 150 OE Set-up Time 20 OE Hold Time 20 Data Set-up Time 50 Data Hold Time 0 Byte Load Cycle 0.2 Last Byte Loaded to Data Polling Output Write Cycle Time Write Cycle Time (IND & MIL) Max Units ns ns ns ns ns ns ns ns ns ns µs µs ms ms
CE tblc WE
OE toes tas ADDRESS VALID tch
PAGE MODE WRITE CHARACTERISTICS Symbol twc tas tah tds tdh twp tblc Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Min 20 100 50 0 150 0.2 Max 10 Unit ms ns ns ns ns ns µs
200
Page Mode Write Wave Form
200 500 10 15
OE
A.C. Write Characteristics WE-Controlled
twp tas
toeh
tah AD-VALID AD-VALID tds AD-VALID tdh BYTE-1 BYTE-2
A0-A5
DATA
BYTE-0
tcs CE
tah
twp WE tds DATA HIGH-Z tblc tdh HIGH-Z twc
Chip Clear Wave Form
The content of the 28C64A may be altered to HIGH by the use of the Chip Clear operation. By setting CE to low, OE to 12 volts, and WE to low, the entire memory can be cleared (written HIGH) within 20 ms. The Chip Clear operation is a latch operation mode. After the Chip Clear star ts, the internal chip timer takes over and completes the clear without CE, OE and WE being held active.
VH VIH
DATA VALID
A.C. Write Characteristics CE-Controlled
toes OE tas ADDRESS VALID tch
VIL VIL VIH
OE
toeh
VIH
CE ts WE tp th
tcs WE
tah
tcw CE tds DATA HIGH-Z tblc tdh HIGH-Z twc
ts= 20 ns tp= 200 ns th= 20 ns VH=12.0 V±0.5V
DATA VALID
Par t Numbers & Order Information 28C64APC-2
TURBO IC PRODUCTS AND DOCUMENTS
1. All documents are subject to change without notice. Please contact Turbo IC for the latest revision of documents. 2. Turbo IC does not assume any responsibility for any damage to the user that may result from accidents or operation under abnormal conditions. 3. Turbo IC does not assume any responsibility for the use of any circuitry other than what embodied in a Turbo IC product. No other circuits, patents, licenses are implied. 4. Turbo IC products are not authorized for use in life support systems or other critical systems where component failure may endanger life. System designers should design with error detection and correction, redundancy and back-up features.
8K x 8 EEPROM
Package J -PLCC P -PDIP S -SOIC T -TSOP
Temperature C -Commercial I -Industr ial M -Militar y
Speed -1 120 ns -2 150 ns -3 200 ns -4 250 ns
Rev. 3.0 - 10/28/ 01
Turbo IC, Inc. 2365 Paragon Drive, Suite I, San Jose, CA 95131 Phone: 408-392-0208 See us at www.turbo-ic.com
Fax: 408-392-0207
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