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Part: 29C010C-1
Category:
Memory
Description:
Company: Turbo IC, Inc.
Datasheet: Download 29C010C-1 datasheet File size : 39 kB
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Turbo IC, Inc.
29C010
ADVANCE INFORMATION
HIGH SPEED CMOS 1 Megabit PROGRAMMABLE and ERASABLE ROM 128K X 8 BIT FLASH PEROM
FEATURES: · 120 ns Access Time · 5 Volt Only Reprogramming · Sector Program Operation Single Cycle Reprogram (Erase & Program) 1024 Sectors (128 bytes/sector) Internal Address and Data Latches for 128 Bytes · Automatic Sector Programming Operation Internal Control Timer · Fast Program Times Page Program Cycles: 10 ms Typical Time to Rewrite Complete Memory: 10 s Typical Byte Program Cycle Time: 80 µs · Software Data Protection · Low Power Dissipation 60 mA Active Current 100 µA CMOS Standby Current · Direct Microprocessor End of Program Detection Data Polling · High Reliability CMOS Technology Endurance: 10,000 Cycles Data Retention: 10 years · CMOS and TTL Compatible Inputs and Outputs · Single 5V ± 10% Power Supply for Read and Programming Operations · JEDEC Approved Byte Pinout DESCRIPTION: The Turbo IC 29C010 is a 128K x 8 Flash programmable and erasable read only memory (PEROM) fabricated with Turbo IC's proprietary, high reliability, high performance CMOS technology. Its 1024K bits of memory are organized as 128K by 8 bits. The device offers access time of 120 ns with power dissipation below 330 mW. The 29C010 has a 128 bytes sector program operation enabling the entire memory to be programmed typically in less than 10 seconds. During a program operation, the address and a complete sector (128 bytes) of data are internally latched, freeing the address and data bus for other microprocessor operations. The programming process is automatically controlled by the device using an internal control timer. Data polling on I/O7 or a Toggle bit can be used to detect the end of a programming cycle. In addition, the 29C010 includes an user-optional software data write mode offering additional protection against unwanted (false) write. The 29C010 does not require a separate high voltage to program the device. 5 volts is all that is required.
PIN CONFIGURATIONS:
A12 A16 VCC NC 2 1 WE 32 31 3029 28 27 26 25 24 23 A14 A13 A8 A9 A11 OE A10 CE I/O7 NC NC A16 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 54 6 7 8 9 10 11 3 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 GND I/O4 I/O6 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A9 A13 NC VCC A16 A12 A6 A4
A11 A8 A14 WE NC A15 A7 A5 4 6 8 10 12 14 16
1 3 5 7 9 11 13 15
A15
2
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE CE I/O6 I/O4 GND I/O1 A0 A2
A10 I/O7 I/O5 I/O3 I/O2 I/O0 A1 A3
12 22 21 13 14 15 16 17 18 19 20
I/O2
I/O3
I/O5
32 pins TSOP
32 pins PLCC
32 pins PDIP
Turbo IC, Inc.
29C010
ADVANCE INFORMATION
PIN DESCRIPTION
ADDRESSES (A0 - A16) The Addresses are used to select an 8 bits memory location during a program or read operation. CHIP ENABLE (CE) The Chip Enable input must be low to enable all read/program operations on the device. By setting CE high, the device is disabled and the power consumption is extremely low with the standby current below 100 µA.
OUTPUT ENABLE (OE) The Output Enable input activates the output buffers during the read operations. WRITE ENABLE (WE) The Write Enable input initiates the programming of data into the memory. DATA INPUT/OUTPUT (I/O0-I/O7) Data Input/Output pins are used to read data out of the memory or to program Data into the memory.
DEVICE OPERATION
READ The 29C010 is accessed like a static RAM. Read operations are initiated by both CE and OE on low and terminated by either CE or OE returning high. The outputs are at the high impedance state whenever CE or OE retur ns high. The two line control architecture gives designers flexibility in preventing bus contention. PROGRAM CHIP CLEAR A program cycle is initiated when CE and WE are low and OE is high. The address is latched internally on the falling edge of the CE or WE, whichever occurs last. The data is latched by the rising edge of CE or WE, whichever occurs first. Once a programming cycle has been started, the internal timer automatically generates the program sequence to the completion of the program operation. SECTOR PROGRAM OPERATION The device is reprogrammed on a sector basis. When a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte that is not loaded during the programming of its sector will be erased to read FFh. The programming operation of the 29C010 allows 128 bytes of data to be serially loaded into the device and then simultaneously written into memory during the internally generated program cycle. After the first byte has been loaded, successive bytes of data must be loaded until the full sector of 128 bytes is loaded. Each new byte to be written must be loaded within 300 µs of the previously loaded byte. The sector address defined by the addresses A7 - A16 is latched by the first CE or WE falling edge which initiates a program cycle and they stay latched until the completion of the program cycle. Any changes in the sector addresses during the load-program cycle will not affect the initially latched sector address. Addresses A0 - A6 are used to define which bytes will be loaded within the 128 bytes sector. The bytes may be loaded in any order that is convenient to the user. The content of a loaded byte may be altered at any time during the loading cycle if the maximum allowed byte-load time (300 µs) is not exceeded. All the 128 bytes of the page are serially loaded and are programmed in a single 10 ms program cycle DATA POLLING The 29C010 features DATA Polling to indicate the completion of a program cycle to the host system. During a program cycle, an attempted read of the last byte loaded into the page will result in the complement of the loaded byte on I/O7, i.e., loaded 0 would be read 1. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may be started. DATA Polling may begin at any time during the programming cycle. The content of the entire memory array of the 29C010 may be altered to HIGH by the use of the CHIP CLEAR operation. By setting CE to low, OE to 12 Volts, and WE to low, the entire memory array can be cleared (written HIGH) within 20 ms. The CHIP CLEAR operation is a latch operation mode. After CE, WE, and OE get the CHIP CLEAR process started, the internal chip timer takes over the CHIP CLEAR operation and CE, OE, or WE becomes free to be used by the system for other purposes. HARDWARE DATA PROTECTION The 29C010 has three hardware features to protect the written content of the memory against inadvertent programming: a) Vcc threshold detector - If Vcc is below 3 V the program capabilities of the chip is inhibited for whatever input conditions. b) Noise protection - A WE, OE, or CE pulse of less than 10 ns in width is not able to initiate a program cycle. c) Write inhibit - Holding OE at low, or CE at high, or WE at high inhibits the program cycle. SOFTWARE DATA PROTECTION The 29C010 offers a software controlled data program protection feature. The device is delivered to the user with the software data protection DISABLED, i.e., the device will go to the program operation as long as Vcc exceeds 3 V and CE, WE, and OE inputs are set at program mode levels. The 29C010 can be automatically protected against an accidental write operation during power-up or power-down without any external circuitry by enabling the software data protection feature. This feature is enable after the first program cycle which includes the software algorithm. After this operation is done the program function of the device may be performed only if every program cycle is preceded by the software algorithm. The device will maintain its software protect feature for the rest of its life, unless the software algorithm for disabling the protection is implemented. TOGGLE BIT In addition to DATA Polling the 29C010 provides another method for determining the end of a programming or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
Turbo IC, Inc.
29C010
ADVANCE INFORMATION
SOFTWARE ALGORITHM The 29C010 has an internal register for the software algorithm which enables the memory to provide the user with additional features: a) Software Data Protect Enable A sequence of the three dummy data writes to the memory will activate internal EEPROM fuses during the first page write cycle. These EEPROM fuses will reject any write attempts of new pages of data, unless the three dummy data writes are repeated at the beginning of any page writes. The timing for the dummy data and addresses must be the same as for a normal program operation. A violation of the three steps program protect sequence in data or address timing and content will abort the procedure and reset the device to the starting point condition. Note: Software data protect enable procedure must be performed as part of a standard program cycle. If no additional page data is added to the three dummy data writes, the software data protect enable procedure will be aborted. The data protect state will be activated at the end of the program cycle. 128 bytes of data must be loaded during a Software Data Protection Enable cycle. Table 1 shows the required procedure for enabling the software data protect: TABLE 1 ADD.A14-A0 5555 Hex 2AAA Hex 5555 Hex Address STEP 1 2 3 4 5 6 MODE Page Write Page Write Page Write Page Write Page Write Page Write TABLE 3 ADD.A14-A0 5555 Hex 2AAA Hex 5555 Hex 5555 Hex 2AAA Hex 5555 Hex DATA I/O 7-0 AA Hex 55 Hex 80 Hex AA Hex 55 Hex 10 Hex C) Software Chip Clear The software algorithm of 29C010 includes a sequence of six step dummy data writing to perform a chip clear operation. Table 3 shows the six step wr ite sequence to perform the software chip clear operation:
At the end of the six step program sequence shown in Table 3, the device automatically activates its internal timer to control the chip erase cycle; typically takes 20 msec. After a software chip clear operation has been completed, all 1024K bit locations of memory show high level at read operation mode. d) Software Autoclear Disable Mode This software algorithm disables the internal automatic clear before a program cycle. Table 4 shows the six steps needed to perform the autoclear disable mode. TABLE 4 MODE ADD.A14-A0 Page Write 5555 Hex Page Write 2AAA Hex Page Write 5555 Hex Page Write 5555 Hex Page Write 2AAA Hex Page Write 5555 Hex Page Write Address
STEP 1 2 3 4-131
MODE Page Write Page Write Page Write Page Write
DATA I/O 7-0 AA Hex 55 Hex A0 Hex Sector Data (128 Bytes)
b) Software Data Protect Disable The software algorithm of 29C010 includes a six step sequence dummy data programming sequence to disable the software data protect feature described in a). The six step sequence shown in Table 2 must be performed at the beginning of a program cycle. A violation of the six step program sequence in data or address timing and content will abort the procedure and reset the chip to the starting point condition. After a software data protect disable cycle including the six step sequence has been perfor med, the 29C010 does not require the use of three dummy loads described in a) for the following program cycle. The device is at the software data protect disabled state. Note: When six step sequence of software data protect disable procedure is performed, if no additional bytes of data is added after the six-step write sequence, the software data protect disable procedure will be aborted. The data protect state will be deactivated at the end of the program period. 128 bytes of data must be loaded during a Software Data Protection disable cycle. Table 2 shows the required procedure for disabling the software data protect: TABLE 2 ADD.A14-A0 5555 Hex 2AAA Hex 5555 Hex 5555 Hex 2AAA Hex 5555 Hex Address
STEP 1 2 3 4 5 6 7-134
DATA I/O 7-0 AA Hex 55 Hex 80 Hex AA Hex 55 Hex 40 Hex Sector Data (128 Bytes)
Program operation using the software autoclear disable mode will reduce programming time to typically 40 µs per byte. The program cycle using software autoclear disable mode is usually used after a chip clear or a software chip clear operation. At the end of the six step sequence, the autoclear before program is disabled and will stay that way unless a powerdown occurs or the software autoclear enable procedure is initiated. e) Software Autoclear Enable Mode Automatic page clear before page program can be restored to 29C010 either by Vcc power-down or by software autoclear enable mode. Table 5 shows the six step page procedure needed to enable software autoclear mode: TABLE 5 MODE ADD.A14-A0 Page Write 5555 Hex Page Write 2AAA Hex Page Write 5555 Hex Page Write 5555 Hex Page Write 2AAA Hex Page Write 5555 Hex Page Write Address
STEP 1 2 3 4 5 6 7-134
MODE Page Write Page Write Page Write Page Write Page Write Page Write Page Write
DATA I/O 7-0 AA Hex 55 Hex 80 Hex AA Hex 55 Hex 20 Hex Sector Data (128 Bytes)
STEP 1 2 3 4 5 6 7-134
DATA I/O 7-0 AA Hex 55 Hex 80 Hex AA Hex 55 Hex 50 Hex Sector Data (128 Bytes)
Turbo IC, Inc.
29C010
ADVANCE INFORMATION
(C) = COMMERCIAL ( I ) = INDUSTRIAL (M ) = MILITARY
ABSOLUTE MAXIMUM STRESS RANGES * TEMPERATURE Storage: Under Bias: -65° C to 150° C -55° C to 125° C
D.C. CHARACTERISTICS Symbol Parameter Condition Icc Active Vcc Current
Min
Max Units 60 70 90 100 200 3 (C) (I) (M) (C) (I&M) mA mA mA µA µA mA
ALL INPUT OR OUTPUT VOLTAGES with respect to Vss +6 V to -0.3 V * "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Range: Commercial: Industr ial: Militar y: 5 V ± 10% 10,000 Cycles/Byte (Typical) 10 Years 0° C to 70° C -40° C to 85° C -55° C to 125° C
Isb1
Isb2
CMOS Standby Current TTL Standby CE=Vih, OE=Vil, Current All I/O Open, Other Inputs=Vcc Max Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Vin=Vcc Max
CE=OE=Vil; All I/O Open, Min Read or Write Cycle Time CE=Vcc-0.3 V to Vcc+1 V
Iil
1
µA
Iol
10
µA
Vil Vih Vol Voh
-0.1
-0.8
V V V V
Vcc Supply Voltage: Endurance: Data Retention:
2 Vcc+0.3 Iol=2.1 mA Ioh=-0.45 mA 2.4 0.45
A.C. CHARACTERISTICS - READ OPERATION
29C010-1 29C010-2 29C010-3
Symbol tacc tce toe tdf toh
Parameters Min M a x Min M a x Min M a x Address to 120 150 200 Output Delay CE to Output 120 150 200 Delay OE to Output 70 80 90 OE to Output 0 40 0 50 0 60 In High Z Output Hold 0 0 0 from Address Changes, Chip Enable or Output Enable Whichever Occurs First
Unit ns ns ns ns ns A.C. TEST CONDITIONS Output Load : 1 TTL Load and Cl=100 pF Input Rise and Fall Times : < 10 ns Input Pulse Level : 0.45 V to 2.4V
A.C. Read Wave Forms
ADDRESS ADDRESS VALID tacc tce tdf toe OE toh OUTPUT HIGH-Z OUTPUT VALID HIGH-Z
CE
Turbo IC, Inc.
29C010
ADVANCE INFORMATION
A.C. WRITE CHARACTERISTICS Symbol tas tah tcs tch tcw twp toes toeh tds tdh tblc tlp twc Parameter Address Set-up Time Address Hold Time Write Set-up Time Write Hold Time CE Pulse Width WE Pulse Width OE Set-up Time OE Hold Time Data Set-up Time Data Hold Time Byte Load Cycle Last Byte Loaded to Data Polling Output Write Cycle Time Min 20 100 0 0 100 100 10 10 50 0 0.2 Max Units ns ns ns ns ns ns ns ns ns ns µs µs ms
300 500 10
A.C. Write Wave Forms WE-Controlled
OE
toes tas
toeh
ADDRESS
VALID tch
tcs CE
tah
twp WE tds DATA HIGH-Z tblc tdh HIGH-Z twc
DATA VALID
A.C. Write Wave Forms CE-Controlled
toes OE tas ADDRESS VALID tch toeh
tcs WE
tah
twp CE tds DATA HIGH-Z tblc tdh HIGH-Z twc
DATA VALID
Others parts begin by 29
29-1 29-2 29-3
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