|
|
Part: J-TYPE
Category:
Timing Circuits
-> Oscillators
-> RF
Description: Voltage Controlled Crystal Oscillator
Company: Vectron International
Datasheet: Download J-TYPE datasheet File size : 522 kB
Request For quote: Find where to buy J-TYPE
Datasheet text preview:
Product Data Sheet
J-Type
Voltage Controlled Crystal Oscillator
Features
· Output Frequencies from 1.024 MHz to 170.000 MHz · +3.3 or +5.0 volt options · Small 14mm x 9mm J-type Package · CMOS or PECL Outputs · Low phase noise and custom options · 0/70° C or 40/85° C operating temperature · Tri-State output (CMOS) Enable/Disable (PECL)
Applications
· Clock Smoothing · Frequency Translation · SONET, SDH, ATM, DSLAM, ADM
Description
The J-type voltage controlled crystal oscillator incorporates VI's advanced VCXO performance capabilities while adhering to a package footprint compatible with the industry-common J-lead package. The J-type VCXO is a quartz stabilized square wave generator with either a CMOS output for driving CMOS/TTL loads or a PECL output. The device is packaged in a 6 pin J-lead ceramic package and is hermetically sealed with a grounded conductive lid.
J-Type Voltage Controlled Crystal Oscillator
CMOS Output Option Electrical Performance @ 25°C for the CMOS output option
Parameter
Supply Voltage1, +5 volt option +3.3 volt option Supply Current Center Frequency, see ordering information Operating Temperature, see ordering info Absolute Pull Range over the operating temperature range, aging and power supply Vc=0.5 to 4.5 at 5V supply or 0.3 to 3.0 V at 3.3V supply see ordering information for options Gain Transfer (Frequency vs. Control Voltage) Output Level High2 Output Level Low2 Output Rise/Fall Time2 Duty Cycle3, see ordering info Control Input Leakage Control Voltage Modulation Bandwidth RMS Jitter, Output=12.0-77.760 MHz RMS Jitter, Output=12.0-77.760 MHz. Band =12.0 KHz - 20 MHz Control Range Maximum Supply Voltage Storage Temperature Soldering Temp./Time
Symbol
Minimum
Typical
Maximum
Unit
Vdc Vdc MHz °C ppm
FN TOP APR
4.5 5.0 5.5 3.0 3.3 3.6 10mA + 0.25mA per MHz, typical 1.024 77.760 0/70, -40/85 ±50 to ±100
KV VOH VOL tR/ tF SYM IL BW 0.8*Vcc
Positive 45/55 or 40/60 10 3 <0.5 1 V V ns % uA kHz ps ps
0.1*Vcc 5
0 TS TLS -55 -
VDD 7 125 220/10
V °C °C/s
1. Power supply bypass is required and a 0.1uF in parallel with a 0.01uF high frequency capacitor is recommended. 2. Figure 1 defines these parameters. Figure 2 illustrates the load used to test devices. 3. Duty cycle is defined as on-time versus period at 1.4 V for TTL, and 2.5 V for CMOS (5volt supply) and at 1.65 V for CMOS (3.3 volt operation)
Pin Out Information for the CMOS output option
Pin
1 2 3 4 5 6
Symbol
Vc Tri-State1 GND Output CMOS/TTL select1,2 VCC
Function
VCXO Control Voltage. TTL logic low disables output TTL logic high, or no connect, enables output Case and electrical ground. VCXO Output TTL logic low optimizes symmetry for CMOS TTL logic high, or NC, optimizes symmetry for TTL. Power Supply Voltage (5.0 V or 3.3V ±10%)
1. Standard option. Tri-State can be connected to pin 5 and CMOS/TTL select would be on pin 2. 2. Output is HCMOS. For frequencies >12MHz, this option optimizes symmetry for either CMOS or TTL thresholds. Ground this pin for frequencies < 12MHz.
Vectron International · 267 Lowell Road, Hudson, NH 03051 · Tel: 1-88-VECTRON-1 · Fax: 1-888-FAX-VECTRON
2
J-Type Voltage Controlled Crystal Oscillator
CMOS Output Option
Figure 1 Output Wave Form Figure 2 Output Test Conditions
Threshold = 1.4 volts for TTL and 50% for CMOS
Output Test Conditions (25±5°C) for 5 volt devices. For 3.3V use 15pF cap only, no resistors needed.
Ordering Information for the CMOS output option (add frequency)4
Package Supply Voltage
C 5V±10%
VCXO Type
U VCXO G
APR (ppm)
±50 C
Operating Temp. (°C)
0/70 A
Output/Duty Cycle Min/Max
TTL/ CMOS 45/55%1 CMOS 45/55%2 CMOS 40/60%3
Tri-State
Specials
J
6 pin Ceramic SOJ
T Tri State on pin 2
N
Standard
D 3.3V±10% L
±10% N linear VCXO H
±80
L
-40/85
J
±100
K
1. Output is CMOS and symmetry is tested at TTL and CMOS thresholds. 2. Output is CMOS and symmetry is tested at CMOS threshold. This option is used for 3.3 V operation. 3. Output is CMOS and symmetry is tested at CMOS thresholds. This option is required for 3.3V, frequencies >51.840MHz. 4. Note: Not all combinations are possible.
Example: JDUGCKTN @ 77.76 MHz = 3.3 volt, VCXO@77.760, ±50 ppm APR, 0/70°C, 40/60% Symmetry, CMOS, Tri-State on pin 2.
Standard Frequencies, in MHz, for CMOS output option
1.024 3.686 6.144 8.448 14.318 19.44 27.000 38.880 52.000 1.544 4.000 6.176 10.000 15.360 20.000 30.000 40.000 65.536 2.000 4.032 6.312 12.000 15.440 20.480 32.000 40.960 77.760 2.048 4.096 6.400 12.288 16.000 24.000 32.768 44.736 155.5201 3.088 4.434 8.000 12.352 16.384 24.576 34.368 50.000 3.580 5.000 8.192 13.000 18.432 24.704 35.328 51.840
1. Uses a PLL multiplier, jitter is 25ps rms typical vs 3ps rms typical for a HFF (High Frequency Fundemental) design. Available with 5 Vdc input only. Other frequencies available upon request.
Vectron International · 267 Lowell Road, Hudson, NH 03051 · Tel: 1-88-VECTRON-1 · Fax: 1-888-FAX-VECTRON
3
Others parts begin by j0
J0-1
|
|
|
