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Part: AN201
Category:
Description: High-performance Multiplexing With The DG408
Company: Vishay Intertechnology
Datasheet: Download AN201 datasheet File size : 83 kB
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AN201
Vishay Siliconix
High-Performance Multiplexing with the DG408
The DG408 and DG409, new multiplexers from Vishay Siliconix, represent a new generation of high-performance multiplexers and demultiplexers with many specific improvements over existing products available today. Built with the company's high-voltage silicon-gate technology, these new ICs offer significantly reduced on-resistance (<100 W), leakage currents (IS(OFF) < 0.5 nA), power dissipation (2.25 mW), and much faster switching (250 ns) over older industry standards. These improved specifications allow designers to greatly reduce system errors and improve system performance. The DG408 and DG409 will enhance two primary multiplexer and demultiplexer applications: communications and telemetry. Important multiplexer specifications depend on the application and the accuracy required by the system. For example, in communications, switching speed is important; whereas, in telemetry, on-resistance, charge injection, and output capacitance are critical because they determine the accuracy of the system. This article will present examples of these types of applications and discuss the benefits that these new multiplexers bring to their system performance.
teed to be more than four times faster than previously available (1 ms) multiplexers. Its guaranteed break-before-make time (10 ns) prevents crosstalk during switching transitions.
IN1
DG408
DG408
OUT
Communications The digital telephone exchange is a communication multiplexed system. In this type of system (see Figure 1), a number of telephone channels carrying speech are sequentially switched (i.e., multiplexed) for fixed periods of time into an analog-to-digital converter. Once converted to a digital form, the different speech signals can be processed and routed within the exchange. A typical specification for the voice bandwidth in a telephone exchange is 3.3 kHz. For this bandwidth, an 8-kHz sampling rate is sufficient (i.e., sampling rate > 2 times the bandwidth). Therefore, each sampling period is 125 ms, during which time, each of the 32 channels of the multiplexer must be addressed. This means that each channel will be turned on for 3.906 ms (125 ms/32). This figure is ideal, since the multiplexer cannot switch in zero time. Depending on the particular multiplexer used, there will either be an overlap between sampling pulses (i.e., make-before-break switching), which leads to crosstalk between channels, or a separation between samples (i.e., break-before-make switching), which reduces the sampling time of a particular channel and results in lower multiplexer efficiency. The DG408 has switching times (250 ns) guaran-
DG408
DG408
IN32
Address Bus
FIGURE 1. 32-Channel Multiplexed System
Document Number: 70600 05-Aug -99
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AN201
Vishay Siliconix
Telemetry a 1000-pF load. For low-level signals, this offset may be excessive. Using a differential multiplexer, such as the DG409, will provide at least an order of magnitude improvement in the total offset error.
Telemetry offers many applications for multiplexer and demultiplexer combinations. A telemetry system uses transducers (a device which converts a physical variable, such as pressure, flow, temperature, etc. to an electrical equivalent) to measure variables, which are fed back via a multiplexer, monitored, and acted upon if necessary.
Figure 2 shows the position of a multiplexer in a high-performance, closed-loop telemetry system. The transducer output generally produces an analog output (which may need preamplification and filtering prior to multiplexing). With a wide variety of transducer types available, the inputs to the multiplexer may take many forms, including high-frequency, dc, high-level, low-level, voltage, current, and differential signals. Whether a signal requires preconditioning before being multiplexed depends on the total accuracy required of the system.
High-level signals become a potential problem at different values, depending on the technology used to manufacture the multiplexer. For a CMOS multiplexer, high-level signals greater than the positive and negative supplies must be avoided to prevent permanent damage to the device. If the supplies are exceeded by the analog signal, the inherent source/drain-to-supply diodes (Figure 3) will become forward biased.
When the expected overloads have a short duration, usually a couple of switching diodes used in series with the supply leads will prevent permanent damage by blocking the flow of reverse current in the power supply loads.
Because the multiplexer follows the transducer output, the multiplexer specification will have a significant bearing on the system accuracy. For example, a low-level signal can, potentially, require preamplification. A primary source of error with a low-level signal may be the switching transients present in the multiplexer. These transients are the result of charge injection from the switches, producing an error voltage (usually positive for a CMOS switch) which appears at the multiplexer output. Hence, the lower the signal level, the greater the error introduced by the charge injection of the switch.
For example, the DG408 with its 20-pC (typical) charge injection will create a 20-mV offset error when switching into
Differential signals can be generated by bridge-type transducers. These devices will produce a signal of two components: a common-mode signal which is large and a small difference signal. It is the difference component that conveys the measurement information. Figure 4 shows the DG409 differential multiplexer being buffered by a full differential amplifier which rejects the unwanted common-mode voltage. The amplifier output consists solely of the differential signal. The ability of the differential multiplexer to reject unwanted common-mode voltages makes it especially useful in systems where pick-up of electrical noise is a concern.
Transducers
Multiplexer
DG408
Demultiplexer
DG408
Link A/D Converter Processor D/A Converter
FIGURE 2. Position of the Multiplexer in a Telemetry System
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Document Number: 70600 05-Aug -99
AN201
Vishay Siliconix
+V S V
buried layer which prevents the formation of the inherent SCR found in CMOS structures. This immunity to latch-up makes the DG408/409 particularly insensitive to transient conditions which could occur in a remote multiplexer environment. Figure 5 shows a typical profile, including the inherent parasitic components. Under specific conditions (inputs exceeding the supplies), one or more of the pn junctions becomes forward biased and, under normal conditions, would result in the pnpn structure turning on. This would appear as a short circuit across the supply and would persist until the power was removed or the device burned up. Using the "buried layer", the gain of the pnpn structure has been reduced to less than unity. This effect makes device latch-up virtually impossible.
Control +V D V
FIGURE 3. CMOS Switch Showing Inherent Diodes
High-frequency signals above a couple of MHz can limit system accuracy, whether its specific channel is on or off. When the device is turned on, the signal is filtered to some degree by the distributed resistance and capacitance of the signal path through the multiplexer. When the device is turned off, the high frequency couples with adjacent channels through the "off" channel to the output, thereby adding to the system error.
Accuracy Errors introduced by a multiplexer can be split into dc and ac components. Steady-state errors in a multiplexer are due to the on-resistance and finite leakage of the switch. Two sources of dc error can be quantified by input offset = RS where RS = source resistance IS = source leakage rDS(on) = on-resistance ID(on) = drain on-state leakage. IS(off)
What Makes the DG408/409 a Good Multiplexer? Choosing a technology for a multiplexer can depend on many factors, including the environment, its ruggedness, the accuracy required, and the cost. The choice is often a compromise between these factors. The DG408/409 is fabricated with high-voltage CMOS technology developed specifically by Vishay Siliconix to enhance the analog switch/multiplexer range. The processing steps include a
DG409
S1A 100 kW +V 100 kW S4A 100 kW LM101D + S1B 100 kW V Difference Signal Out
S4B
Address
FIGURE 4. Differential Multiplexer
Document Number: 70600 05-Aug -99 www.vishay.com
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AN201
Vishay Siliconix
n-Channel S V Silicon Gate S
p-Channel Silicon Gate
D
D V+
p+
n+
n+
p+
n+
p+
p-Well Expitaxial Layer (n) p+ Buried Layer
n Substrate
FIGURE 5. Cross Section of a High Voltage Silicon Gate CMOS Device
Multiplexer rDS(on) ID(on)
Thermo Couple Strain Gauge
Amplifier IBIAS + A/D Converter Link Processor
Reference Voltage DG408
Demultiplexer
Pump
Meter
DG408
FIGURE 6. Typical Data Aquisition System
Figure 6 shows a typical data multiplexing system. Because the multiplexer feeds a very high impedance, its input offset is a function of its on-resistance and the on-state leakage of the switch plus the amplifier bias current.
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VOFFSET = rDS(on)
For the DG408/409 typical specifications, this offset will be VOFFSET = 100 (500 pA + 30 pA) = 53 nV
Document Number: 70600 05-Aug -99
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ÉÉÉ
p+ D/A Converter
ÉÉÉ
n+
Link
(ID(on) + I(BIAS))
AN201
Vishay Siliconix
This typical offset (at 25_C) should be compared with the signal level to determine whether the error introduced by the offset is acceptable. the greater the number of channels, the slower the speed due to additional capacitance at the common output node. The DG408/409 switching speed (tTRANS) is 250 ns maximum at room temperature with a 10-ns minimum break-beforemake time. While this break-before-make time prevents overlap or "alias" between channels, it reduces multiplexer efficiency and, therefore, is kept as short as possible. A channel-switching rate (Figure 8) is defined for the DG408/409 by tON, tOFF, and tSAMPLE, where tSAMPLE is dependent on the application.
Another source of error that may be introduced by the switch occurs when the switch changes state. Transients (due to capacitive coupling between the drivers and drain) can be manifested as an error voltage appearing on the output node. The effect of charge injection is measured in volts and is given by
V = Qi/C
where
Qi is the injected charge in picocoulombs C is the load capacitance at the output.
Channel 1 tON tSAMPLE tOFF
The DG408/409 devices have been internally compensated to minimize the effects of the injection. This is achieved by including compensation capacitors on the output switch. These capacitors are sized to produce an equal and opposite transient which tends to cancel out the effect of the switch injection. Typical charge injection for the DG408/409 is 20 pC for the test configuration shown in Figure 7.
Channel 2
FIGURE 8. Channel Switching Rate
RSOURCE
VSOURCE
DG408
VSOURCE = 0 V RSOURCE = 0 W
VO 10 nF
Assuming a tSAMPLE of 1.2 ms, the maximum switching rate for the DG408/409 (with no pulse-edge overlap) is once every 1.5 ms or a frequency of 666 kHz. This example shows that the switching speed of the DG408/409 is not a significant factor unless the tSAMPLE time becomes much smaller. For multi-channel systems, if the sampling theorem is obeyed, the maximum switching rate will limit the number of channels and/or the maximum frequency components of any of the channel inputs. Techniques are available to improve the switching rate, and an example using the DG408/409 and DG400 will be shown later.
VO Address SW Off Switch On SW Off
D VO
Versatility With CMOS switches, signal conduction is the same in either direction. Therefore, as shown in Figure 9, it's possible to use the DG408 as a demultiplexer with one input from the digital-to-analog converter and 8 outputs.
FIGURE 7. Charge Injection Test Circuit
OUT1
Switching Speed
Multiplexers operate in real time (i.e., samples are taken sequentially and represent the analog input signal). Obviously, the quicker a multiplexer changes state, the more samples can be taken in a given time. Fast switching operation is often difficult to achieve using larger multiplexing devices. That is,
Document Number: 70600 05-Aug -99
Digital Output From Processor
D/A Converter
DG408
OUT8
FIGURE 9. Using the DG408 as a Demultiplexer
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AN-1 AN-2 AN-3 AN-4 AN-5 AN-6 AN-7 AN-8
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