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Part: AN204
Category:
Description: Serially-controlled 8-Channel Analog Switch Array Simplified
Company: Vishay Intertechnology
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AN204
Vishay Siliconix
Serially-Controlled 8-Channel Analog Switch Array Simplifies Signal Conditioning and Routing
When analog signals are processed in a digital system, some of the processing must be performed in the analog domain, both before and after the digital portion of the system. CMOS analog switches are frequently used in a variety of analog signal conditioning functions under digital control, such as gain ranging, anti-aliasing filter corner-frequency selection, sample-and-hold functions, input channel selection, input summing, and signal routing. A new serially-controlled array of precision CMOS switches simplifies the design of these functions, while improving system accuracy and reducing component count and board space. This application note presents simplified solutions for some of these digitally controlled analog signal processing circuits using the new DG485 eight-channel serially-controlled switch array. has eight switches on a chip, and through a unique serial data control architecture, any combination of the eight switches can be connected to a common output line.
A New Way to Control a Switch Array The internal block diagram for the DG485 is shown in Figure 1. It consists of five elements: (1) the logic input stages, (2) an array of eight D-type flip-flops that form an input shift register, (3) an array of eight data latches, (4) eight switch drivers, and (5) eight CMOS analog switches. There are three power supply inputs and a ground. The three supplies are V+, V, and VL. V+ and V set the analog range for the signals being controlled by the switches. The range of operation for V+ and V is "5 V to "20 V and also includes single-supply operation by connecting V to ground. The VL input determines the logic switching threshold recognized by the logic input buffer stages. The nominal operating value for VL should be 5 V to allow for TTL-compatible operation (VINL v0.8, VINH w 2.4 V). However, VL can be operated anywhere from 5 to 40 V to facilitate compatibility with a wide range of logic levels. The GND, although being the only ground point on the device, is generally considered to be a digital ground, rather than an analog ground, for the purpose of avoiding ground loops.
The DG485 Switch Array CMOS analog switches typically come in single, dual, and quad configurations. CMOS multiplexers combine up to sixteen switches on a chip, with decoding logic that allows the selection of one switch at a time. Now there is a new function that combines the best of both types of devices. The DG485
VL
TTLIN Z
D Type D Q CLK R
Latch D Q CLK Q
DIN
A
Driver Z A Z
Switch A A
S1
Z CLK A
D Type D Q CLK R
Latch D Q CLK Q
Driver Z A Z
Switch A A
S2
Z LD A
Z RS A D Type D Q CLK R Latch D Q CLK Q DOUT Driver Z A Z Switch A A S8 D
FIGURE 1. The DG485 Internal Block Diagram
Document Number: 70602 10-Aug-99 www.vishay.com S FaxBack 408-970-5600
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AN204
Vishay Siliconix
(1) (2) Shift Register (3) Address Register (4) (5)
Level-Shift V+
Level-Shift CMOS Switch
VL Data Input GND
DD Type Flip1 Q Flop RS CLK
S D Latch CLK Q Z Z D
RS CLK
LD
V
FIGURE 2. Simplified Schematic of a Typical DG485 Channel
A simplified schematic of a typical DG485 channel which details its five elements is shown in Figure 2.
on hard. The result is a fairly flat on-resistance as the analog voltage of the source (or drain) ranges from V+ to V. Typically, a ±8 W variation is seen.
The input buffer stages (1) are CMOS inverters which have ESD protection consisting of catch diodes and a resistor to dissipate the energy generated by electrostatic discharge, which can destroy an MOS input. The scheme used in the DG485 provides protection in excess of "4000 V on all pins of the device. (This protection is required only on the logic inputs because the power supply and output connections have built-in protection via the large parasitic p-n junctions.) The TTL input buffers are CMOS inverter stages that swing between VL and GND, and drive a level shift stage to drive the D-type master-slave flip flops (2) that swing from V+ to GND. The D-type flip-flops have master-slave inverters with edge-sensitive clocking, and they form the data input shift register. Their outputs are connected to the address register latches (3), which are single-stage clocked-inverter flip-flops with level-sensitive clocking. These latches, in turn, are connected to the switch drivers (4), which provide level translation from the latch outputs, which swing between V+ and GND, to the gates of the CMOS switches (5), which must swing from rail to rail. These switches are pairs of large p-channel MOSFETs in parallel with complementary n-channel MOSFETs; this parallel combination has a low on-resistance of 85 W: (maximum at 25_C). The p-channel device is turned on by driving its gate to the V rail, and it is turned off by driving its gate to the V+ rail. In an opposite manner, the n-channel device is turned on by driving its gate to V+ and turned off by driving its gate to V. These parallel switches compensate for each other's increase in on-resistance as the analog signal approaches either rail. That is, as the VGS for one device goes to zero, it shuts off, while the opposite polarity device is fully enhanced or turned
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Controlling the Array with a Serial Data Bus The DG485 connects to the serial output of a microprocessor system, as shown in Figure 3. The eight CMOS switches in the DG485 are controlled via the serial data output via the DIN (data in) pin. Data is loaded into the eight-bit shift register with each clock pulse at the CLK (clock) input. The contents of the shift register are loaded into the octal latch when a logic "high" signal is applied to the LD (load) input. The octal latch holds the state (on or off) of the individual switches in the array. The RS (reset) input resets the octal latch to all "zeroes" when a logic "low" is applied, turning all switches off with a subsequent LD command.
Analog-Signal Voltage Ranges The power supplies for the device are V+, V, and VL. The analog signal range of the switches is defined by the power supply rails. Because the DG485 is built on a 44 V silicon-gate CMOS process, rail-to-rail signal swings are possible. The power supply voltages range from "5 V to "20 V, and single-supply operation is allowed from +5 V to +40 V. The logic levels are set with VL input. With 5 V applied to VL, TTL and 5 V CMOS logic compatibility (VINL = 0.8 V, VINH = 2.4 V) is assured.
Document Number: 70602 10-Aug-99
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AN204
Vishay Siliconix
S1 S2 S8
DG485 +15 V 15 V +15 V 8085 V+ Switch Array V VL Octal Latch GND D
DIN SOD Shift Register
DOUT
To Next Switch Array
ALE Data Bus 8212
LD
CLK
RS
(8) (8) Address Bus Decoder 8205
WR R/S
FIGURE 3. The DG485 Simplifies Analog Signal Control With a Serial Data Bus. The Input Shift Register in the DG485 Receives Switch On/Off-State Data Directly From the Serial Data (SOD) Line from the Microprocessor.
Switch Array with Improved Speed and Accuracy
specifications for the DG485 array and the DG508A multiplexer are compared in Table 1.
In addition to being a useful new function, the DG485 features analog switches with vastly improved performance. They are part of the DG400 family which uses a new silicon-gate CMOS process designed to achieve improved speed, lower power, lower on-resistance, lower leakage, and improved ESD tolerance. These benefits are the result of the inherent reduced overlap parasitic capacitance of silicon-gate CMOS processing.
TABLE 1.
Key Specification (@ 25_C)
Fabrication Process On-resistance (rDS(ON) Max.)
DG508A 8-Channel Multiplexer
44 V Metal-Gate CMOS 450 W 5 nA 1 ms (1000 ns) 59 mW (59000 mW) 500 V
DG485 8-Channel Array
44 V Silicon-Gate CMOS 85 W 1 nA 200 ns 105 mW 4000 V
For comparison of switch performance, key specifications for the industry-standard DG508A eight-channel multiplexer and the DG485 eight-channel array are shown in Table 1. The closest standard IC to the DG485 is the eight-channel DG508A multiplexer. While the DG485 array allows any combination of eight switches to be turned on at one time (compared with the one-of-eight decoding of the multiplexer), it also has improved speed and accuracy with reduced power dissipation. Key
Document Number: 70602 10-Aug-99
Leakage (IS(off) Max.) Switching Time (t(tran) Max.) Power Dissipation (PD Max.) ESD Tolerance
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AN204
Vishay Siliconix
(a) VIN + (b) VOUT S1 + S2 S1 S3 D S2 S3 S8 Continuous S8 DG485 DG485
FIGURE 4. Gain Ranging and Attenuator Circuits
Digitally Controlled Signal Conditioning Input signal conditioning functions like gain ranging, programmable attenuation, and variable filter time constant circuits have one thing in common they use analog switches for selecting various resistor values. There are many ways to create digitally controlled gain stages using CMOS switches. Using the DG485, as shown in Figure 4a, places the analog switch in series with a high-impedance point, such as the input of an op amp, to eliminate errors associated with switch on-resistance. Additionally, the gain value is determined by the ratio of the gain-setting resistors rather than their absolute value. Thus, the accuracy of the gain setting is a function of the matching or scaling of the resistors, independent of resistor or analog switch variations. If matched or monolithic resistor arrays are used, excellent gain accuracy and low gain drift is achieved with this architecture. The DG485 allows for selection of eight different resistor ratios under serial control, and its any-combination-of-eight architecture also allows 255 different parallel combinations of resistor ratios for additional gain ranges. A variation on this theme, shown in Figure 4b, provides programmable attenuation. Again, the analog switches are placed in series with a high-impedance point (the op amp input) to eliminate the effect of switch resistance variations. Attenuation values are selected according to the ratio of the resistors in the string. Digitally Controlled Filter The programmable filter circuit shown in Figure 5 selects resistors rather than capacitors to change the RC time constant of the low pass. This is a useful function at the input of a data acquisition or digital signal processing system which allows the processor to adjust the corner frequency of
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its anti-aliasing filter if various sample rates are being used. Only one capacitor is required, and resistors (which are generally low in cost and easier to specify for accuracy and ratios) are selected with the DG485 to generate different filter characteristics. Resistors that are matched to the ones in the feedback loop are switched at the input of the integrator to maintain unity passband gain for any of the four corner frequencies selected. In this filter topology, unlike the gain-ranging circuit shown above, the analog switches are placed in series with the time-constant setting resistors. Therefore, the resistance characteristics of the switches play a significant role in the accuracy of the time constant selection. Switches with low on-resistance are preferred since the time constant of the filter is (rDS(on) + Rf) C. If Rf is large, compared to the 85-W on-resistance of the DG485, accurate filter break frequencies may be selected via digital serial control. RIN is chosen according to the dc gain requirement of the system. For example, dc unity gain inversion is achieved with RIN = Rf. The break frequency, f3dB, is calculated as
f 3dB + 1 2pRC
The actual measured 3 dB frequencies may vary as much as 10% due to the parasitic drain and source capacitance of the DG485 switches and the variation in on-resistance seen from channel to channel. Because any combination of the eight switches can be selected, there are a total of sixteen different RC values that can be programmed by using parallel resistor combinations for a wide range of filter roll-offs.
Document Number: 70602 10-Aug-99
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AN204
Vishay Siliconix
C = 10,000 pF S1 S2 S3 S4 R2 R3 R4 VIN f3db = 1/(2pRC) 15 V 0.1 mF S6 S7 S8 LF356 + +15 V 0.1 mF VOUT R1
Code to Shift Register
R2
1
R1 S5 R3 R4 R1 = 1.6 kW R2 = 800 W R3 = 530 W R4 = 400 W 1 0 0 0
2
0 1 0 0
3
0 0 1 0
4
0 0 0 1
5
1 0 0 0
6
0 1 0 0
7
0 0 1 0
8
0 0 0 1
f3 d b
10 kHz 20 kHz 30 kHz 40 kHz
FIGURE 5. Programmable Low Pass Filter
RIN V1 V2 S1 DOUT S2 LD D Rf +15 V + CLK V8 S8 DIN 15 V V17 V18 S1 DOUT S2 LD D Clock VOUT = (V1 + V2 + ... Vn) For Rf = RIN Load V VOUT
DG485
#1
DG485
#3 V24 S8 DIN
CLK
Serial Data In
FIGURE 6. The summing-node mixer is frequently used in audio production consoles. Inputs are switched on and off with the summing node of the DG485.
Switching, Selecting, and Summing Multiple Inputs
Frequently a system will process signals from multiple inputs. Time division multiplexing takes samples of each input in successive time intervals. The traditional approach is a multiplexer followed by a sample-and-hold circuit. The DG485 simplifies this function while allowing faster data throughput
and higher precision. The channel selection is accomplished with a serial data line, eliminating the latches that are required with a multiplexer, such as the DG508A, when interfacing with the data bus. In addition, the sample-and-hold function is covered by the DG485 with a hold capacitor. The reduced on-resistance and faster transition time of the DG485 allows faster sample acquisition, and the low leakage reduces droop rate.
Document Number: 70602 10-Aug-99
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