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Part: AN207
Category:
Description: 15-ns DG611 Switch Family Combines Benefits of CMOS And Dmos
Company: Vishay Intertechnology
Datasheet: Download AN207 datasheet File size : 56 kB
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AN207
Vishay Siliconix
12-ns DG611 Switch Family Combines Benefits of CMOS and DMOS Technologies
The DG611, DG612, and DG613 are extremely low-power, high-speed analog switches designed to optimize circuit performance in high-speed switching applications. Each of these devices integrates low-power CMOS drivers with high-speed DMOS FETs. The resulting switches boast some remarkable features: high speed, low power, low on-resistance, low leakage, low charge injection and low channel capacitance, all on the same device.
Circuit Description
Each device has four independently controlled switches. The DG611 and DG612 respond to opposite control logic. The DG611 has a normally closed (NC) function while the DG612 is a normally open (NO) device. The DG613 offers a complementary function. It contains two NO and two NC switches. This versatile device can be configured as two single-pole single-throw (SPDT), one double-pole double-throw (DPDT), a "T" switch, two "L" switches, and so forth. As illustrated in Figure 2, each analog switch channel consists of an input stage, followed by a level translator, a driver stage, and an n-channel MOSFET. The input stage is a CMOS inverter powered from VL. VL is the logic power supply voltage (normally +5 V). As with any classic CMOS inverter, control input pin impedance is very high and essentially equivalent to the logic input pin capacitance (approximately 5 pF). This pin does not draw current (except for leakage) when in a steady state. To change states it is necessary to charge or discharge this input capacitance, which requires a short current pulse from the control logic gate.
By combining both CMOS and DMOS technologies on a single chip, the DG61X family avoids the tradeoffs inherent in other high-speed analog switches, such as high power consumption, high on-resistance, and high channel capacitance. The DG61X family is likewise superior to DMOS FETs, which are fast but highly sensitive to electrostatic discharge, as well as requiring external drivers built with a number of external discrete components.
This application note describes the new DG61X devices in detail and provides a series of application hints which will help you take full advantage of this fast new family in your designs.
S1, 4
D1, 4
IN1, 4
S1-4
D1-4
S1-4
D1-4
S2, 3
D2, 3
IN1-4
IN1-4
IN2, 3
DG611
Normally Closed
DG612
Normally Open
DG613
Complementary
All Switches Shown for Logic "0" Inputs.
FIGURE 1. Functional Diagrams (Typical Switch)
Document Number: 70605 03-Aug-99
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AN207
Vishay Siliconix
VL
V+ S
V D
IN DMOS Switch
Driver V Input Logic Level Translator
FIGURE 2. Typical Channel Block Diagram
The level translator provides level shifting of the 0 to 5 V logic input to the V+ to V voltage excursions needed to control the MOSFET switch. The driver stage acts as a buffer and provides current amplification to quickly charge/discharge the MOSFET gate, thus quickly turning the switch ON or OFF. The switching element is an n-channel double-diffused enhancement-mode MOSFET. DMOS FETs achieve very low inter-electrode capacitance and high speed, thanks to their lateral construction. To turn the switch ON, a voltage equal to V+ is applied to the FET's gate. This enhances the channel into conduction. The source and Drain terminals can stand up to 16 V with respect to the substrate voltage (V). ESD protection diode pairs are connected from each logic input, source, and drain pin to the V+ and V- power supply rails.
becomes a challenge. ATE limitations (lead inductances/capacitances, generator's rise and fall times) conspire to slow things down. This is why the tON/tOFF specifications on the data sheet are so loose (35 ns max). A typical device in a typical application is much faster than the data-sheet specifications would indicate. A bench test circuit reduced test fixture parasitics, while a low capacitance (3 pF) FET probe was used to monitor the output voltage. Figure 3 shows that before the output starts to change there was a propagation delay through the driver of about 8 ns. Once the FET starts to turn on, the output voltage rises very fast. The rise time was approximately 2 ns. Total tON (50% Vin to 90% Vout) was approximately 12 ns. Similarly at turn-off the driver 's propagation delay appeared to be about 8 ns, the fall time was about 5 ns. tOFF (50% VIN to 90% VOUT) was about 7 ns.
Reduced Switching Transients By adding two dynamic compensation capacitors to the output driver stage, charge injection glitches have been virtually eliminated. For comparison purposes, Figure 4 illustrates the typical charge injection characteristics for two Vishay Siliconix' high-speed analog switches: DG271 and DG611. Note how flat the DG611 characteristic is. This guarantees low charge injection regardless of analog signal voltage. Charge injection causes switching glitches both at turn-on and at turn-off times. To evaluate and compare the switching glitches produced by the DG611, the test circuit of Figure 5 was built. A 4-Vp-p triangular bipolar wave form was fed to the switch input. On this wave form we wanted to cut some 0-V notches as commanded by a pulse train. 100-ns pulses were used to interrupt signal flow twice in every period letting the output voltage to fall to 0 V.
Document Number: 70605 03-Aug-99
Optimized Characteristics
The DG611 family was designed to optimize the parameters which are most important in high-speed applications.
Switching Speed Discrete DMOS FETs such as the SD210 or SD5000 are well known for their fast switching speeds. In fact, both specify a td(on) of 1 ns max. The DG611 family combines fast DMOS switching elements with a low-power CMOS driver. These devices are so fast that measuring their speed at final test
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AN207
Vishay Siliconix
S +2 V D VOUT
VIN
300 W
CL = 3 pF
50 W
Test Circuit
VIN
VOUT
FIGURE 3. Bench Test Switching Times Are Faster Than Data Sheet Limits
As seen in Figure 6, there were significant differences between the DG271 and the DG611 output wave forms. First, the DG611 considerably reduced switching glitches. Some spikes went from 1 V to 0.2 V, a fivefold improvement. Second, the faster DG611 reduced output delays and produced more consistent notch widths.
On-Resistance A low on-resistance switch reduces measurement errors and helps to achieve fast settling times in test equipment and data acquisition systems. It is also useful in reducing insertion loss when switching RF or video signals. The DG611 family specifies a typical rDS(on) of 18 . This is one of the lowest values among high-speed analog switches. In order to reduce parasitic capacitances, the DG611 uses an n-channel enhancement mode MOSFET for the switch element. Consequently, its on-resistance increases as the channel voltage increases. Eventually, as VS approaches V+ the n-channel MOSFET loses its enhancement voltage (V+) -VS and turns off.
For general purpose switches, it is customary to assume that all charge injection is due to capacitive coupling from the output driver into the analog channel. At the low Qinj levels achieved by the DG61X family, even the spurious capacitance (due to pin proximity from the logic control pin to the adjacent drain pin) will contribute a significant amount of charge. For this reason, it is possible to get minimal glitches by applying the input signal to the drain pin and using the source pin for the output.
Document Number: 70605 03-Aug-99
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AN207
Vishay Siliconix
80 60 40 a) DG271 20 0 20 40 60 15 10 5 0 5 10 15 CL = 1000 pF 50 W b) DG611 50 W a) V+ = 15 V, V = 15 V b) V+ = 15 V, V = 3 V VS
DG271 or DG611 VOUT
Charge Injection (pC)
1 kW
Ideal (0 pC) VIN
VS Source Voltage (V)
FIGURE 4. The DG611 Charge Injection Characteristic Shows a Dramatic Improvement Over That of the DG271
FIGURE 5. Switching Spikes Evaluation Circuit
VS
VIN
VOUT
a) Using DG271
a) Using DG611
FIGURE 6. The DG611 Significantly Improves the Output Wave Form
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Document Number: 70605 03-Aug-99
AN207
Vishay Siliconix
600 +5 V 500 a) 400 r DS(on) ( W ) GND V 300 IN D S 200 a) V+ = 5 V b) V+ = 12 V c) V+ = 12 V, ISD = 10 mA b) c) VL V+ ISD V+ V+
VS
100
V V
0 0 2 4 6 8 10 12 14 16 18 20
VS Source Voltage (V)
FIGURE 7. Typical rDS(on) Characteristics
FIGURE 8. ESD Protection Diodes are Located at all Control and Switch Pins
Figure 7 illustrates typical on-resistance curves. Curve (a) represents single 5-V operation. Assuming a maximum acceptable rDS(on) value of 200 , the usable analog signal range goes from 0 V to slightly over 2 V. Curve (b) shows operation with V+ = 12 V. Now the usable signal range has increased to 8 V. If you want to operate in the flat, low-resistance part of the curve, you may want to limit your analog signal to no more than 6 V. Curve (c) was generated using a 10-mA ID current. Note that when VS = 12 V, it still shows an rDS(on) = 480 . To sink 10 mA, VD has gone down to 7.2 V, and this creates a partial channel enhancement.
High-Speed 8-Channel Analog Multiplexer
If you are designing a high-speed data acquisition system, then you will need a very fast analog multiplexer. A fast multiplexer like the DG408 specifies a typical transition time of 160 ns. By using the DG611 to make the multiplexer shown in Figure 9, you will achieve transition times in the 30-ns range, a sixfold speed improvement. This added speed will allow you to achieve sampling rates in excess of 3 MHz, as demonstrated below.
ESDS (ESD Sensitivity) By incorporating a CMOS driver in front of the DMOS FET, direct access to the DMOS gate has been eliminated. By itself, this goes a long way to reduce ESD sensitivity. Additional ESD protection diodes have been added to the source and drain pins. Nevertheless, to maintain high speed, a compromise between ESD protection, speed, on-resistance, and on-capacitance had to be reached. This means that the protection diodes are relatively small and protect only up to about 500 V. To prevent damage from high-energy electrostatic fields, anti-static handling precautions must be observed at all times.
For an 8-channel multiplexer the maximum sampling rate is given by:
fS +
8
1 (t SETTLING ) tTRANS) rD S ( o n ) C(on)
(1)
where tSETTLING = N
(2)
for an accuracy of 0.01% (12 bits) N = 9.
For small signals, let us assume that typical rDS(on) = 18
Applications
The output node capacitance is given by: Following is a collection of practical application hints and design ideas intended to help you design with the DG61X family.
Document Number: 70605 03-Aug-99
C(on) = 1 CD(on) + 7 CD(off) = 10 pF + 7
2 pF = 24 pF
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