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Part: AN208
Category:
Description: a High-Performance, Low Cost Analog Switch Family
Company: Vishay Intertechnology
Datasheet: Download AN208 datasheet File size : 56 kB
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AN208
Vishay Siliconix
A High-Performance, Low-Cost Analog Switch Family
Introduction Vishay Siliconix' popular DG201 quad analog switch has been an industry workhorse for over two decades. To meet the demands of new applications for more precision and faster switching speeds, an improved version of the DG201, along with five other general purpose analog switches, is being introduced by Vishay Siliconix. The new "B" series provides lower switch on-resistance, leakage current, turn-on time, charge injection, and power consumption at prices comparable to industry-standard devices. Behind these improved levels of performance is Vishay Siliconix' new high-voltage silicon gate process, HVSG-II. HVSG-II substantially increases the switch's overall performance, allowing analog signals to be switched efficiently from 20 V to +3 V. Even though these devices were designed
on a high-voltage process, they still exhibit very good low-voltage performance and provide a single-supply solution. T h e s e general-purpose parts are ideal for a host of applications, including automatic test equipment, instrumentation, and voice or data communications. This note d e t a i l s performance improvements, and provides a competitive comparison and overview of general applications.
Improved Single-Supply Operation The "B" family can be used with split supplies or a single supply. The DG201B/202B have an internal +5-V regulator. The DG211B and DG212B are ideal for low-voltage single supply operation (+3 V to +5 V).
S
D
S
D
S
D
IN TTL or CMOS TTL or CMOS
IN CMOS
IN
DG201B
Normally Closed, Internal Regulator
DG211B
Normally Closed
DG308B
Normally Closed
S
D
S
D
S
D
IN TTL or CMOS TTL or CMOS
IN CMOS
IN
DG202B
Normally Open, Internal Regulator
DG212B
Normally Open
DG309B
Normally Open
FIGURE 1. "B" Series Diagrams
Document Number: 70606 10-Aug-99
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AN208
Vishay Siliconix
TABLE 1.
DG211B/212B Typical Low-Voltage Performance V+ & VL (V)
+5 +4.5 +4 +3.3 +3 +2.5 +2
devices overcome this problem with reduced channel lengths and parasitic capacitances. These improvements allow the DG211B's turn-on (tON) time to be reduced to 120 ns typical, and power dissipation (PD) to be as low as 0.7 nW during the quiescent condition. Note that both tON and PD are a function of the power supplies used to power the chip. Table 1 shows the correlation between low voltage effects of the supply voltage used. The switching speed is typically 120 ns with split 15-V supplies. It slows to 1600 ns with a mere +2-V single supply. Turn-on time (tON) is measured from 50% of the INPUT logic control to 90% of the analog output signal. This interval includes the delay through the logic translator, FET driver stages, and the FETs themselves. An RC time constant comprised of the channel on-resistance and the output load capacitance (CL) increases tON with an increase in CL. This effect is minimal as long as a shunt resistive load is also present. The increase in tON is approximately equal to:
DtON = rDS(on) CL
Logic Threshold (V)
+2.2 +2 +1.9 +1.6 +1.5 +1.2 +1
tO N (ns)
200 200 300 400 500 900 1600
tO F F (ns)
50 50 50 100 100 200 400
Note: VS = +2 V, RL =1 kW , V = 0 V
Simply connect VL to V+ (Figure 2). The voltage at VL sets the logic threshold (Table 1). Even though the DG211B and DG212B operate as low as +2 V, their turn-on time increases proportionally to the decrease in V+. At +3.3 V these devices are quite suitable for general applications, even though their on-resistance can approach 1 kW . Later it will be shown how this resistance can also be substantially reduced. The DG201B/202B parts also were tested to t+3 V with similar performance (except tON which was slightly slower).
where CL is the value above 35 pF (and 35 pF is the standard CL used to measure tON).
Low On-Resistance On-resistance can make a critical addition to the error budget in precision applications. For the "B" devices, typical rDS(on) is 45 W and is in series with a load resistance RL (Figure 2). The error is equal to
rDS(on)/(rDS(on) + RL) or 45/(45 + 1 k) = 4.3%
1500 V+ = +2 V 1300 +2.5 V +3 V 1100 r DS(on)( W ) 900 700 500 +5 V 300 100 0 1 2 3 4 5 VD Drain Voltage (V) +4 V +3.3 V
Speed Combined With Power Normally the speed of an analog switch can only be increased at the expense of the power driving the chip. But the "B" series
+2 V to +5 V
V+
VL
DG211B
S D RL 1 kW
IN
GND
V
FIGURE 2. DG211B Single-Supply Operation
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FIGURE 3. Low Voltage rDS(on) Curves
Document Number: 70606 10-Aug-99
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AN208
Vishay Siliconix
Increasing RL will proportionally reduce this error. However, a large load resistance reduces the off-isolation. If the analog signal is dc, off-isolation is not a problem since it will not be coupled through the off-channel parasitic capacitor. But if the analog signal is ac, then the off-isolation decreases as the frequency increases or if RL increases. One solution to this problem is to run the switch into the virtual ground of an inverting amplifier, as described below. switch has no real off-isolation at this frequency so the usable bandwidth is really a function of off-isolation. Since off-isolation is 60 dB at 3 MHz, then 3 MHz becomes the maximum usable frequency (assuming that 60 dB is the minimum acceptable limit). This relationship can be seen on the data sheet off isolation vs. frequency curve. At a bandwidth of 1 MHz, the off-isolation is 90 dB. Bandwidth is also associated with insertion loss. This specification is expressed in dB and equals On-Resistance Flatness On-resistance flatness is a measure of the change in rDS(on) when the source or drain voltage varies. This delta can distort the input signal as follows:
DR ON Harmonic Distortion + 20 log RL 20 Log R L ) R ON R ON
The insertion loss of the "B" series devices is generally 6 dB over the usable frequency range from 0 to 3 MHz with RL = 50 W .
Limiting analog signal dynamic range to the flattest part of the rDS(on) curve can reduce this error. A "virtual ground" at the summing junction of an op amp can provide the high impedance required to reduce distortion. If the non-inverting input of an op amp is referenced to ground, a virtual ground appears at the inverting input because the input offset voltage (VOS) of most op amps is in the microvolt or millivolt range. Thus the inverting input is only the value of this input voltage above or below ground. This virtual ground node is also a very high impedance point because
Charge Injection Charge injection consists of the charge (measured in pC) transferred from the digital driver to the analog channel at the time of switching the device to the "off" state. This unwanted charge is normally induced through parasitic gate-to-source or gate-to-drain capacitances. In a sample-and-hold circuit, charge injection will cause an offset error called "hold-step." "B" series switches have glitch suppression circuitry on-chip and fewer parasitics at the gate. These improvements have reduced the typical charge to 1 pC, compared with the industry-standard specification of 20 pC. Tips for reducing charge injection effects
R IN +
VOS IB
where IB is the input bias current of the op amp. For instance, a typical op amp with VOS = 1 mV and IB = 1 nA would have an input impedance of 1 MW .
Bandwidth Improvements The bandwidth of a general-purpose analog switch is generally not specified on most data sheets. Bandwidth can be calculated by this expression:
f 3d b +
1 2pRC
Using the drain instead of the source for the output results in less glitch, but the "step" is slightly greater. This approach, however, isn't without its problems. The logic signal (IN) can be injected into the analog output path by the package interlead capacitance (pin-to-pin) which is generally about 0.75 pF. Another 1-3 pF is usually associated with the PC board stray capacitance, if the INPUT and DRAIN, which are adjacent to each other at the package, are laid out without a ground plane separation. The board used for this test measured about 3 pF of stray capacitance. Because of this interlead and board capacitance ("Cstray"), it is also recommended that the logic amplitude be clamped to about +3 V . The charge current is expressed here:
where R = rDS(on) and C = CD(on), also RL assumed to be infinite. Substituting 45 W and 16 pF, respectively, results in a theoretical calculated bandwidth of [220 MHz. In reality, the
Document Number: 70606 10-Aug-99
I+C
dv dt
where dv is the instantaneous logic voltage change and C is Cstray.
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AN208
Vishay Siliconix
+15 15
0.01 mF
10 mF V+ DG211B V
10 mF
0.01 mF Glitch FET Probe CSTRAY CL 1 nF Polystyrene
15 V to +15 V
S 0.1 mF
D
IN
GND
FIGURE 4. Charge Injection Test Circuit
Charge current (I) can be reduced if dv is reduced, where dv is the logic control signal amplitude. Note, for example, the reduction of current injected into the hold capacitor (CL) shown in Figure 4. A proper ground plane separation or guard, as well as logic clamping, can substantially reduce the charge injection caused by Cstray. A single point ground (with digital and analog grounds separated), or a ground plane, should be used to reduce ground loops and switching noise. Figure 6a depicts the "B" series actual hold-step of 9 mV with +2 V at the source. Maxim's best currently available equivalent device, for example, offers a 14-mV hold-step (Figure 6b) measured at turn-off. To achieve a Q of 1 pC (which is actually 1 mV) using a "B" series device, the voltage at the source should be at ground and the logic amplitude clamped to about +3 V. Or reduce Cstray. The voltage change can be calculated by:
Not Recommended
10 W DC Input 0.1 mF 1000 pF Polystyrene
FET Probe Scope
Recommended
DV +
Q CL
DC Input 0.1 mF 1 nF to 10 nF Polystyrene
FET Probe Scope
A 10-W damping resistor in series with the hold capacitor (Figure 5), actually increases the effects of charge injection. The load becomes more resistive. CL could be increased to about 10 nF, which would help suppress the glitch and hold-step (while decreasing the droop rate in S/H circuits).
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FIGURE 5. Reducing Charge Injection Effects
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Document Number: 70606 10-Aug-99
AN208
Vishay Siliconix
Faster Turn-on Times For the "B" series, typical leakage current at room temperature has been improved from 20 pA to only 10 pA. On-resistance and leakage are critical in determining circuit accuracy. Drain-on leakage for "B" series devices has been reduced to 20 pA from the industry-standard 150 pA. This current directly increases the error or voltage drop across the channel. This error increases the circuit offset voltage. The error is calculated by: Verror = rDS(on) Improved On-Resistance and Leakage Current For the "B" series parts, on-resistance is substantially reduced from 115 W to 45 W , which also reduces the above error. While CL can be increased to reduce glitch, this approach can be a problem in sample-and-hold circuits. There is a trade-off between acquisition time and droop-rate. An increase in CL slows the droop-rate but increases the acquisition time. The droop-rate can be understood as the voltage change caused by the sum of D the drain-off leakage current (ID(off)), D the capacitor leakage (IC), which is caused by the dielectric absorption of the capacitor, and D the bias current (IB) if a buffer amplifier is used after the hold capacitor CL. or, ID ( o n )
In the new "B" series, tON has been reduced from 480 ns to 120 ns. Maxim's best currently available equivalent device, by comparison, has both a slower tON and a glitch with a very slow recovery time (Figure 6b). Parts like this need a 1.0-ms de-glitcher to make them usable. Of course, this "solution" also adds to the cost of implementation. The "B" series parts require only 300 ns to settle out (Figure 6a).
Power Consumption The power dissipated by the DG211/212B devices has been reduced to t1 nW typical. Competing devices range from 400 nW to 18 mW. The combination of high speed and low power consumption is a unique feature of the new "B" series. Power consumption is equal to
(V+)(I+) + (V)(I) + (VL)(IL)
dv + ID(off) ) I B ) I C CL dt
which is a quiescent condition calculation. This can be added to the channel power when the switch is in a dynamic state. The power consumed by the analog channel is determined by I2R where (I) is the current through the channel and (R) is rDS(on).
VS = 0 V+ = + 15 V V = 15 V CL = 1000 pF 1 = Logic Input Control (Logic "1" = Off) 2 = VS 3 = VD 9 mV
14 mV
a) DG201B Glitch and Hold Step due to Charge Injection
b) Competitor M's DG201A Glitch and Hold Step
FIGURE 6.
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