|
|
Part: IRM7001
Category:
Description: SIR Modulator/demodulator
Company: Vishay Intertechnology
Datasheet: Download IRM7001 datasheet File size : 52 kB
Request For quote: Find where to buy IRM7001
Datasheet text preview:
IRM7001
SIR Modulator/Demodulator
Dimensions in inches (mm)
A .393 (10.0) .386 (9.8) 16 1 9 B .157 (4.0) .244 (6.2) 8 .150 (3.8) .229 (5.8)
SOIC Package
.050 (1.27) BSC .068 (1.75) .054 (1.35) T .019 (.49) .014 (.35) .009 (.25) .004 (0.1)
R x 45° .009 (.25) .008 (.19) .049 (1.25) 7 ° .016 (.40)
FEATURES · Compliant with IrDA 1.0 Physical Layer Specifications · Interfaces with IrDA 1.0 Compliant IR Transceivers · Used in conjunction with Standard 16550 UART · Transmits/Receives either 1.6”s or 3/16 Pulse Mode · Internal or External Clock Mode · Programmable Baud Rate · 2.75.5 V Operation · 16 Pin SOIC Package APPLICATIONS · Interfaces with IR Transceivers in: - Computer Applications: PDAs Dongle or other RS232 Adapter - Telecom Application: Modems Fax Machines Pagers - Handheld Data Collection: Industrial Medical Transportation DESCRIPTION The IRM7001 SIR-Encoder/Decoder is a CMOS modulator/ demodulator chip that is used to both encode and decode information as per the IrDAź SIR (Serial InfraRed) signal modulation and demodulation scheme. This chip is designed to work with Infineon IrDA compatible transceivers and all other IrDA compatible transceivers. The chip contains a clock divider circuit used to generate the 16X clock internally. This makes it very suitable for microcontroller-based embedded system design.
Notes: 1. Dimensions A and B are datums and T is a datum surface. 2. Dimensioning and tolerancing per ansi Y14.5M, 1982 3. Controlling dimension: millimeter. 4. Dimension A and B do not include mold protrusion. 5. Maximum mold protrusion 0.15 (0.005) per side.
Figure 1. IRM7001 pin out
IRM - 7001
16XCLK TXD RCV A0 A1 A2 CLK_SEL GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OSCIN OSCOUT PWR DN PLS MOD IR_TXD IR_RCV NRST
Figure 2. IRM7001 Block Diagram
TXD
SIR ENCODE
IR_TXD
/NRST RCV SIR DECODE IR_RCV
INT_CLOCK A0 A1 A2 16XCLK PULSEMOD CLK_SEL
CLOCK DIVIDE
Document Number: 82576 Revision 17-August-01
www.vishay.com
1
Figure 3. IRM7001 Usage Scenario (with Internal Clock)
IRM7001 IRMS/T6118 IRM5000 11 10 RxD OSCIN OSCOUT IR_TXD TXD 3 4 IO 1 5 6 IO 2 IO 3 3.6864MHz 15 14 2 TxD
Figure 4. IRM7001 Usage Scenario (with External Clock)
IRMS/T6118 IRM5000 IRM7001 2 TxD 11 10 RxD IR_RCV RCV 16XCLK CLK_SEL IR_TXD TXD 3 1 VCC BAUDOUT SOUT Microprocessor/ Controller
Microprocessor/ Controller SOUT
SIN
IR_RCV RCV A0 A1 CLK_SEL A2
SIN
Table 1. Selection of Internal Clock Rate from Crystal Oscillator
Selected Clock Rate (bps) 115200 57600 19200 9600 38400 4800 2400 TEST PURPOSE 0=L, 1=H A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 CRYSTAL FREQ. DIVISION Divided by 2 Divided by 4 Divided by 12 Divided by 24 Divided by 6 Divided by 48 Divided by 96 No Division
Figure 5. Transceivers IRMS/T6118 and IRM5000 IRMS/T6118
IRM5000
IRM7001 SIR Modulator/Demodulator functions extremely well with Infineon IRMS6118/IRMT6118 and IRM5000 SIR (115 Kb/ s) Infrared Data transceivers. These products provide the user with a low component count and cost effective way of implementing an IrDA port on their products where the microcontroller does not have a built-in IrDA port support
Figures 12, 13, and 14 show the schematic, PCB front side and back side for an IRM5000/7001 based port. Table 7 provides the Bill of Materials list to implement the port. Figures 15, 16, and 17 show the schematic, PCB front and the back side for an IRMS6118/IRM7001 based port. Table 8 provides the Bill of Materials list to implement the port.
Document Number: 82576 Revision 17-August-01
www.vishay.com
2
Table 2. Pin Out and Signal Description
Signal 16X CLK Pin 1 Type DIGIN Description Positive edge triggered input clock signal that is set to 16 times the data transmission baudrate. This clock is used to drive the Encoder/Decoder state machine. Depending on the application, the 16XCLK can be provided by the application circuitry, or the internal clock divider circuitry can be used. Selection of operating mode (Internal or External clock) is selected by the CLK_SEL line. If External clock mode is selected, the application circuitry need not provide an oscillator. Negative edge triggered input signal that is normally tied to the SOUT signal of a UART (serial data to be transmitted). Data is modulated and output as IR_TXD. Output signal normally tied to SIN signal of a UART (received serial data). RCV is the demodulated output of IR_RCV. Clock multiplex signals. These signals are asserted to select the appropriate clock rate to support the following baudrate: 115200, 57600, 38400, 19200, 9600, 4800 and 2400 bps. Active high signal, used to activate either the Internal or External clock. A high on this line activates the External clock (16XCLK), or if it is pulled low, the Internal clock is used. Chip ground DIGIN Active low signal used to reset the IrDA-SIR Decode state machine. Normally this line is tied to the POR (power on reset) line of the circuit or simply to Vcc. In addition to resetting the circuitry, this signal can be asserted to disable any data reception. Input is from the SIR optoelectronics. Input signal is a 3/16th pulse which is demodulated (pulse stretched) to generate the RCV (3) output signal. This signal is the modulated TXD signal. A level high on this input puts the chip into the monoshot transmit mode. In this mode, when there is a negative transition on the TXD input, a rising edge on the internal transmit modulation state machine will activate a high pulse on IR_TXD for 6 crystal clock cycles. With a 3.6864MHz crystal, this corresponds to 1.63us. This mode cannot be used in conjunction with the 16XCLK clock. It is meant to be used with the external crystal clock. By default, this input pin is pulled to GND. A high on this input puts the internal oscillator in POWERDOWN MODE. The internal oscillator normally is not powered down.
TXD RCV A0-A2 CLK_SEL GND NRST
2 3 4-6 7 8 9
DIGIN DIGOUT DIGIN DIGIN
IR_RCV IR_TXD PULSEMOD
10 11 12
DIGIN DIGOUT DIGIN (with pulldown)
POWER-DN
13
DIGIN (with pulldown)
OSCOUT OSCIN VCC Function
14 15 16
ANAOUT ANAIN
Crystal Oscillator input Crystal Oscillator input Power (see Electrical Specifications for detail)
The IRM7001 can be used in conjunction with a microcontroller/microprocessor that has a serial communication interface (UART). Prior to communication the processor selects the transmission baudrate by selecting appropriate levels on the A0-A2 lines. This process sets up the communication system to operate at the prescribed data rate. After this initial step, serial data can be transmitted or received at the prescribed data rate. The IRM7001 consists of two state machinesthe SIR Encode and SIR Decode blocks, and a sequential block Clock Divide, which synthesizes the required internal signal INT-CLOCK, based on the inputs A0-A2 and the CLK_ SEL line. The IRM7001 can be placed into Internal Clock Mode (CLK_SEL set to low) or External Clock Mode (CLK_ SEL set to high). The internal clock signal INT_CLOCK source is then gated appropriately through to the INT_CLOCK signal. In application where the external 16XCLK signal is provided, there is no need to provide an oscillator.
The SIR Encode block is driven by TXD (negative edge triggered signal), which initiates the modulation state machine, resulting in the modulated IR_TXD signal (which drives the SIR compatible electronics). The SIR Decode block is driven by the IR_RCV signal (negative edge triggered signal, derived from the optoelectronics). IR_RCV is demodulated by the SIR Decode block resulting in the RCV signal, which represents the stretched input pulse. In addition, there is a pin provided to the user, called the PULSEMOD. A high level input on this pin activates the 1.6us mode on the IR_TXD. In this mode, whenever there is a negative edge on the TXD, the rising edge on the modulation state machine will set the IR_TXD signal high for 6 crystal clock cycles no matter what the selection on A2, A1 and A0 lines is. With a crystal frequency of 3.6864MHz, this corresponds to a high pulse of 1.63us.
Document Number: 82576 Revision 17-August-01
www.vishay.com
3
Others parts begin by ir
IR-1 IR-2 IR-3 IR-4 IR-5 IR-6 IR-7 IR-8 IR-9 IR-10 IR-11 IR-12 IR-13 IR-14 IR-15 IR-16 IR-17 IR-18 IR-19 IR-20 IR-21 IR-22 IR-23 IR-24 IR-25 IR-26 IR-27 IR-28 IR-29 IR-30 IR-31
|
|
|
