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Part: Si7840DP-DS

Category:

Description: Ds-spice Model For Si7840DP

Company: Vishay Intertechnology

Datasheet: Download Si7840DP-DS datasheet     File size : 338 kB

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Datasheet text preview:
SPICE Device Model Si7840DP
Vishay Siliconix
N-Channel 30-V (D-S) Fast Switching MOSFET
CHARACTERISTICS
· N-Channel Vertical DMOS · Macro Model (Subcircuit Model) · Level 3 MOS · Apply for both Linear and Switching Application · Accurate over the -55 to 125°C Temperature Range · Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics
DESCRIPTION
The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125°C temperature ranges under the pulsed 0-to-10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70671 30-Aug-01 www.vishay.com
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SPICE Device Model Si7840DP
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static
Gate Threshold Voltage On-State Drain Current
a
Symbol
Test Condition
Simulated Data
1.2 529 0.0076 0.0115 43 0.75
Measured Data
Unit
VGS(th) ID(on)
a
VDS = VGS, ID = 250µA VDS 5V, VGS = 10V VGS = 10V, ID = 18A VGS = 4.5V, ID = 15A VDS = 15V, ID = 18A IS = 4.1A, VGS = 0V
V A 0.0077 0.0115 40 0.75 S V
Drain-Source On-State Resistance Forward Transconductance Diode Forward Voltage
a a
rDS(on) gfs VSD
Dynamic
b
Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time
Qg Qgs Qgd td(on) tr td(off) tf trr IF = 4.1A, di/dt = 100 A/µs VDD = 15V, RL = 15 ID 1A, VGEN = 10V, RG = 6 VDS = 15V, VGS = 5V, ID = 18A
15.4 3.8 6 14 19 36 62 45
15.5 3.8 6 17 14 39 19 50 Ns nC
Notes a. Pulse test; pulse width 300 µs, duty cycle 2%. b. Guaranteed by design, not subject to production testing.
www.vishay.com
2
Document Number: 70671 30-Aug-01
SPICE Device Model Si7840DP
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 70671 30-Aug-01
www.vishay.com
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