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Details, datasheet, quote on part number:VG36128401BTL-7H
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| Part: | VG36128401BTL-7H |
| Category: | Memory => DRAM |
| Description: | Desc = 8Mx16 4B ;; Speed Grade = -6/-7H/-7L/-8H ;; FEATURES(REFRESH) = Syn. (4K) ;; PACKAGEPIN-WIDTH, Type = 54-400 Mil Tsopii |
| Company: | Vanguard Microelectronics Limited |
| Datasheet: | Download VG36128401BTL-7H datasheet File size : 1367 kB |
| Request For quote: | Find where to buy VG36128401BTL-7H
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Datasheet text preview:
VIS
Description
4 (word x bit x bank), respectively.
VG36128401B / VG36128801B / VG36128161B CMOS Synchronous Dynamic RAM
The VG36128401B, VG36128801B and VG36128161B are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 x 4 x 4, 4,194,304 x 8 x 4 and 2,097,152 x 16 x
The synchronous DRAMs achieve high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII or 54-ball VFBGA (x16 only).
Features
· Single 3.3V ( 0.3 V ) power supply · High speed clock cycle time -6: 166MHz, -7H: 133MHz, -7L:133MHz, -8H: 100MHz · Fully synchronous operation referenced to clock rising edge · Possible to assert random column access in every cycle · Quad internal banks controlled by BA0 & BA1 (Bank Select) · Byte control by LDQM and UDQM for VG36128161B · Programmable Wrap sequence (Sequential / Interleave) · Programmable burst length (1, 2, 4, 8 and full page) · Programmable /CAS latency (2 and 3) · Automatic precharge and controlled precharge · CBR (Auto) refresh and self refresh · X4, X8, X16 organization · LVTTL compatible inputs and outputs · 4,096 refresh cycles / 64ms
. Document :1G5-0183 Rev.5 Page 1
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Pin Configurations
VG36128401 (x4) VG36128801 (x8) VG36128161 (x16) VDD NC VDDQ VDD DQ0 VDDQ VDD DQ0 VDDQ DQ1 DQ2 VSSQ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
VG36128401B / VG36128801B / VG36128161B CMOS Synchronous Dynamic RAM
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC
VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC VSS NC DQM CLK CKE NC
NC NC DQ1 DQ0 VSSQ VSSQ DQ3 NC NC DQ4 NC DQ2 VDDQ VDDQ VDDQ DQ5 NC NC DQ6 DQ1 DQ3 VSSQ VSSQ VSSQ DQ7 NC NC VDD VDD VDD NC NC LDQM WE /WE WE /CAS /CAS /CAS /RAS /RAS /RAS /CS /CS /CS BA0(A13) BA0(A13) BA0(A13) BA1(A12) BA1(A12) BA1(A12) A10 A10 A10 A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD
A11
A9 A8 A7 A6 A5 A4 VSS
A11
A9 A8 A7 A6 A5 A4 VSS
A11
A9 A8 A7 A6 A5 A4 VSS
Pin Descriptions Pin Name CLK CKE /CS /RAS
/CAS /WE DQ0 ~ DQ15
Function Master Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O
Pin Name DQM A0-11 BA0,1 VDD VDDQ VSS VSSQ
Function DQ Mask Enable Address Input Bank Address Power Supply Power Supply for DQ Ground Ground for DQ
Document :1G5-0183
Rev.5
Page 2
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VFBGA BALL ASSIGNMENT (Top View, x16 Only)
A1 Corner
VG36128401B / VG36128801B / VG36128161B CMOS Synchronous Dynamic RAM
1
2
3
4
5
6
7
8
9
A B C D E F G H J
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
DQ8
NC
VSS
VDD
LDQM
DQ7
UDQM
CLK
CKE
CAS#
RAS#
WE#
NC
A11
A9
BA0
BA1
CS#
A8
A7
A6
A0
A1
A10
VSS
A5
A4
A3
A2
VDD
54 Balls 10x9 mm
0.80 mm Ball Pitch
Ball Descriptions Ball Out Pin Name F2 CLK F3 CKE
Function Master Clock Clock Enable
Ball Out F1, E8
Pin Name
Function Address Input
UDQM, LDQM DQ Mask Enable
H7, H8, J8, J7, A0-11 J3, J2, H3, H2, H1, G3, H9, G2 G7, G8 A9, E7, J9 A7, B3, C7, D3 A1, E3, J1 A3, B7, C3, D7 BA0,1 VD D VDDQ VSS VSSQ
G9 F8 F7 F9
/CS /RAS /CAS /WE
Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O
Bank Address Power Supply Power Supply for DQ Ground Ground for DQ
A8, B9, B8, C9, DQ0 ~ DQ15 C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2
Document :1G5-0183
Rev.5
Page 3
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