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Details, datasheet, quote on part number:VG3617161ET-8
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| Part: | VG3617161ET-8 |
| Category: | Memory => DRAM |
| Description: | Desc = 1Mx16 2B ;; Speed Grade = -6/-7/-8 ;; FEATURES(REFRESH) = Syn. (4K) ;; PACKAGEPIN-WIDTH, Type = 50-400 Mil Tsopii |
| Company: | Vanguard Microelectronics Limited |
| Datasheet: | Download VG3617161ET-8 datasheet File size : 1340 kB |
| Request For quote: | Find where to buy VG3617161ET-8
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Datasheet text preview:
VIS
Description
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
The VG3617161ET is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V power supply. This SDRAM is delicately designed with performance concern for current high-speed application. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.
Features · Single 3.3V +/- 0.3V power supply · Clock frequency:166MHz, 143MHz, 125MHz · Fully synchronous with all signals referenced to a positive clock edge · Programmable CAS Iatency (2,3) · Programmable burst length (1,2,4,8,& Full page) · Programmable wrap sequence (Sequential/Interleave) · Automatic precharge and controlled precharge · Auto refresh and self refresh modes · Dual internal banks controlled by A11(Bank select) · Simultaneous and independent two bank operation · I/O level : LVTTL interface · Random column access in every cycle · X16 organization · Byte control by LDQM and UDQM · 4096 refresh cycles/64ms · Burst termination by burst stop and precharge command
Document:1G5-0189
Rev.2
Page 1
VIS
Pin Configuration
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
50-Pin Plastic TSOP(II)(400 mil)
VD D
DQ0 DQ1
1 2 3 4 5 6 7
50 49 48 47 46 45 44
VSS
DQ15 DQ14
VSSQ
DQ2 DQ3
VSSQ
DQ13 DQ12
VDDQ
DQ4 DQ5
VD D Q
DQ11 DQ10
VG3617161ET
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
VSSQ
DQ6 DQ7
VSSQ
DQ9 DQ8
VDDQ LDQM WE CAS RAS CS (BS)A11 A10 A0 A1 A2 A3 VDD
VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS
Pin Description (VG3617161ET)
Pin Name A0-A11
Function Address inputs - Row address A0-A10 - Column address A0-A7 A11: Bank select Data-in/data-out Row address strobe Column address strobe Write enable Ground Power
Pin Name LDQM, UDQM
Function Lower DQ mask enable and Upper DQ mask enable
DQ0~DQ15 RAS CAS WE VSS VDD
CLK CKE CS VDDQ VSSQ
Clock input Clock enable Chip select Supply voltage for DQ Ground for DQ
Document:1G5-0189
Rev.2
Page 2
VIS
Absolute Maximum Ratings(1)
VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM
Parameter Voltage on any pin relative to Vss Supply voltage relative to Vss Short circuit output current Power dissipation Operating temperature Storage temperature
Symbol VIN,VOUT VDD,VDDQ IOUT PD TOPT TSTG
Value -1.0 to +4.6 -1.0 to +4.6 50 1.0 0 to + 70 -55 to + 125
Unit V V mA W °C °C
Recommended DC Operating Conditions (TA=0~70°C)
Parameter Supply Voltage Input High Voltage, all inputs Input Low Voltage, all inputs
Symbol VDD VI H VIL
Min 3.0 2.0 -0.3
Typ 3.3
Max 3.6 VDD+0.3 0.8
Unit V V V
Note
I II
Note I.Overshoot limit : VIH(MAX.)=VDDQ+2.0V with a pulse width < 3ns II .Undershoot limit : VIL=VSSQ-2.0V with a pulse width< 3ns and -1.5V with a pulse width< 5ns DC Electrical Characteristics Parameter II L IO L VOH VOL Description Input Leakage Current ( 0 V VI N V D D All other pins not under test = 0V) Output Leakage Current Output disable, ( 0 V V V ) OUT DDQ LVTTL Output "H" Level Voltage(lOUT = -2mA) LVTTL Output "L" Level Voltage(lOUT = 2mA) Min. -5 -5 Max. 5 5 Unit A A Note
2.4 -
0.4
V V
Capacitance (TA=25°C,f=1MHZ)
Parameter Input capacitance(CLK) Input capacitance(all input pins except data pins) Data input/output capacitance
Symbol C11 C12 CI/O
Typ 2.5 2.5 4.0
Max 4 5 6.5
Unit pF pF pF
Document:1G5-0189
Rev.2
Page 3
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