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Details, datasheet, quote on part number:VG3617801BT-8H
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Datasheet text preview:
VIS
Description
VG3617801CT 16Mb CMOS Synchronous Dynamic RAM
The VG3617801CT is CMOS Synchronous Dynamic RAMs organized as 1,048,576-word X 8-bit X 2bank. It is fabricated with an advanced submicron CMOS technology and is designed to operate from a single 3.3V power supply. This is packaged using JEDEC standard pinouts and standard plastic TSOP.
Features
· Single 3.3V( ± 0.3V ) power supply · Clock Frequency:100MHz · Fully synchronous with all signals referenced to a positive clock edge · Programmable CAS Iatency (2,3) · Programmable burst length (1,2,4,8,& Full page) · Programmable wrap sequence (Sequential/Interleave) · Automatic precharge and controlled precharge · Auto refresh and self refresh modes · Dual Internal banks controlled by A11(Bank select) · Simultaneous and independent two bank operation · I/O level : LVTTL interface · Random column access in every cycle · X8 organization · Input/output control by DQM · 2048 refresh cycles/32ms · Burst termination by burst stop and precharge command · Burst read single write option
Document:1G5-0133
Rev.1
Page 1
VIS
Pin Configuration
VDD
DQ0
VG3617801CT 16Mb CMOS Synchronous Dynamic RAM
44-Pin Plastic TSOP(II)(400 mil)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38
VSS
DQ7
VSSQ
DQ1
V SSQ
DQ6
VDDQ
DQ2
VDDQ
DQ5
VSSQ
DQ3
VSSQ
DQ4
VG3617801CT
37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
VDDQ
NC NC WE CAS RAS CS
VDDQ
NC NC DQM CLK CKE NC
(BS)A11 A10 A0 A1 A2 A3 V DD
A9 A8 A7 A6 A5 A4 VSS
Pin Description (VG3617801CT) Pin Name A0-A11 Function Address inputs - Row address A0-A10 - Column address A0-A8 A11:Bank select Data-in/data-out Row address strobe Column address strobe Write enable Ground Power Pin Name DQM Function DQ mask enable
DQ0~DQ7 RAS CAS WE VSS VDD
CLK CKE CS VDDQ VSSQ
Clock input Clock enable Chip select Supply voltage for DQ Ground for DQ
Document:1G5-0133
Rev.1
Page 2
VIS
VG3617801CT 16Mb CMOS Synchronous Dynamic RAM
Block Diagram
CLK CKE
Clock Generator
Address
Mode Register
Row Decoder
Row Address Buffer & Refresh Counter
Bank B
Bank A
Sense Amplifier
RAS CAS WE Control Logic CS Command Decoder
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column Address Buffer & Burst Counter
Column Decoder & Latch Circuit
DQM
DQ
Document:1G5-0133
Rev.1
Page 3
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