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Details, datasheet, quote on part number:VG36256401A
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Datasheet text preview:
VIS
Description
Preliminary
VG36256401A VG36256801A VG36256161A
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 16,777,216 - word x 4 -bit x 4 - bank, 8,388,608 - word x 8 - bit x 4 - bank, or 4,194,304 - word x 16 - bit x 4 - bank. These various organizations provide wide choice for different applications. It is designed with the state-of-the-art technology to meet standard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the performance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.
Features
· Single 3.3V ( ± 0.3V) power supply · High speed clock cycle time : 7.5ns/10ns · Fully synchronous with all signals referenced to a positive clock edge · Programmable CAS Iatency (2,3) · Programmable burst length (1,2,4,8,& Full page) · Programmable wrap sequence (Sequential/Interleave) · Automatic precharge and controlled precharge · Auto refresh and self refresh modes · Quad Internal banks controlled by A13 & A14 (Bank select) · Each Banks can operate simultaneously and independently · I/O level : LVTTL compatible · Random column access in every cycle · x4, x8, x16 organization · Input/Output controlled by DQM, LDQM, UDQM · 8,192 refresh cycles/64ms · Burst termination by burst stop and precharge command · Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0155
Rev.1
Page 1
VIS
Pin Configuration
Preliminary
VG36256401A VG36256801A VG36256161A
CMOS Synchronous Dynamic RAM
VG36256161 X 16 VG36256801 X 8 VG36256401 X 4
VDD DQ0 VDDQ DQ1 DQ2 VDD DQ0 VDDQ NC DQ1 VDD NC VDDQ NC DQ0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS NC VSSQ NC DQ3
VSS DQ7 VSSQ NC DQ6
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11
VSSQ
DQ3 DQ4
VSSQ
NC DQ2
VSSQ
NC
VDDQ
NC NC
VDDQ
NC DQ5
NC
VDDQ
DQ5 DQ6 VSSQ DQ7 VDD LDQM
VDDQ
NC DQ3 VSSQ NC VDD NC
VDDQ
NC DQ1 VSSQ NC VDD NC
VSSQ
NC DQ2 VDDQ NC VSS NC,VREF
VSSQ
NC DQ4 VDDQ NC VSS NC,VREF
VSSQ
DQ10 DQ9
VDDQ
DQ8 VSS NC,VREF
WE CAS RAS CS
WE CAS RAS CS
WE CAS RAS CS
DQM CLK CKE
DQM CLK CKE
UDQM CLK CKE
A14/(BA0) A14/(BA0) A 1 4 / ( B A 0 ) A13/(BA1) A13/(BA1) A13/(BA1) A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD
A12 A11 A9 A8 A7
A12 A11 A9 A8 A7
A12 A11 A9 A8 A7
A6
A5
A4 VSS
A6
A5
A4 VSS
A6
A5
A4 VSS
Pin Description VG36256401/VG36256801/VG36256161 Pin Name Function A0 - A12 A13, A14 DQ0 ~ DQ15 RAS CAS WE V SS V DD Address inputs Bank select Data - in/data - out Row address strobe Column address strobe Write enable Ground Power (+ 3.3V)
Pin Name DQM, LDQM, UDQM, CLK CKE CS VDDQ V SSQ
Function Upper DQ Mask enable, Lower DQ Mask enable Clock input Clock enable Chip select Supply voltage for DQ Ground for DQ
Document : 1G5-0155
Rev.1
Page 2
VIS
Block Diagram
Preliminary
VG36256401A VG36256801A VG36256161A
CMOS Synchronous Dynamic RAM
CLK CKE
Clock Generator
Address
Mode Register
Row Decoder
Row Address Buffer & Refresh Counter
(Bank D) (Bank C) Bank B
Bank A
Sense Amplifier
Command Decoder
RAS CAS WE
Control Logic
CS
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column Address Buffer & Burst Counter
Column Decoder & Latch Circuit
DQM
DQ
Document : 1G5-0155
Rev.1
Page 3
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