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Details, datasheet, quote on part number:WT60P1
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| Part: | WT60P1 |
| Category: | Microcontrollers |
| Description: | Micro-controllers For Monitors Provide Selection in a Range of ROM/ram Size (max. ROM Size 16KBytes, RAM 288Bytes) |
| Company: | Weltrend |
| Datasheet: | Download WT60P1 datasheet File size : 581 kB |
| Request For quote: | Find where to buy WT60P1
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Datasheet text preview:
WT60P1
Digital Monitor Controller
Ver. 1.51 Jul-31-1998
GENERAL DESCRIPTION
The WT60P1 is a MTP (Multiple-Time-Programmable) version of WT60xx microcontroller which is specially designed for digital controlled multi-sync monitor. It contains 8-bit CPU, 16K bytes flash memory, 288 bytes RAM, 14 PWMs, parallel I/O, SYNC processor, timer, one DDC interface (slave mode I2C interface with DDC1), one master/slave I2C interface, two 4-bit A/D converters and watchdog timer.
FEATURES
* 8-bit 6502 compatible CPU, 4MHz operating frequency * 16384 bytes flash memory, 288 bytes SRAM * 8MHz crystal oscillator * 14 channels 8-bit/62.5kHz PWM outputs (8 open drain outputs & 6 CMOS outputs) * Sync signal processor with H+V separation, frequency calculation, H/V polarity detection/control * Three free-running sync signal outputs for burn-in test (64kHz/62.5Hz, 48kHz/75Hz, 31kHz/60Hz) * Self-test pattern generator generates cross hatch picture * DDC interface supports VESA DDC1/DDC2B standard * Master/slave I2C interface * Watch-dog timer (0.524 second) * Maximum 25 programmable I/O pins * One 8-bit programmable timer * Two 4-bit A/D converter * One external interrupt request * Built-in low VDD voltage reset * +5V power supply
PIN CONFIGURATION
40-Pin PDIP
DA2 DA1 DA0 RESET/VPP VDD GND OSCO OSCI PB5/SDA2 PB4/SCL2 PB3/PAT PB2 PB1/HLFI PB0/HLFO PB6/IRQ PC7 PC6 PC5 PC4 PC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSYNC HSYNC DA3 DA4 DA5 DA6 DA7 PA7/HSO PA6/VSO PA5/DA13 PA4/DA12 PA3/DA11 PA2/DA10 PA1/DA9 PA0/DA8 SCL1/PD0 SDA1/PD1 PC0/AD0 PC1/AD1 PC2 GND OSCO OSCI PB5/SDA2 PB4/SCL2 PB3/PAT PB2 PB1/HLFI PB0/HLFO PB6/IRQ PC7 PC6 PC5 PC4 PC3 DA2 DA1 DA0 RESET/VPP VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42-Pin SDIP
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 DA6 DA7 PA7/HSO PA6/VSO PA5/DA13 PA4/DA12 PA3/DA11 PA2/DA10 PA1/DA9 PA0/DA8 SCL1/PD0 SDA1/PD1 PC0/AD0 PC1/AD1 PC2 VSYNC HSYNC DA3 DA4 DA5
* I2C is a trademark of Philips Corporation. * DDC is a trademark of Video Electronics Standard Association (VESA).
Weltrend Semiconductor, Inc.
1
WT60P1
Digital Monitor Controller
Ver. 1.51 Jul-31-1998
PIN DESCRIPTION
Pin No. 40 42
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pin Name
I/O
O O O I
Descriptions
D/A converter 2. Open-drain output. External applied voltage can up to 10V. D/A converter 1. Open-drain output. External applied voltage can up to 10V. D/A converter 0. Open-drain output. External applied voltage can up to 10V. Reset or Vpp. Active low reset input or Vpp for erase/write flash memory. Power supply (+5V). Ground (0V). Oscillator Output. Connects a 8MHz crystal. Oscillator Input. Connects a 8MHz crystal. I/O Port B5 or I2C data pin. This pin can be an I/O port or I2C serial data pin. I/O Port B4 or I2C clock pin. This pin can be I/O port or I2C clock pin. I/O Port B3 or self-test pattern output. When as an I/O port, it is same as PB5. When it is configured to test pattern output, a vedio signal is output. I/O Port B2. When it is an input pin, it has an internal pull-up resistor. When it is an output pin, the source/sink current is 5mA. I/O Port B1 or half frequency input. I/O Port B0 or half frequency output. I/O Port B6 or Interrupt Request . When as interrupt request input, it has an internal pull high resistor. When as an I/O port, it is same as PB3. I/O Port C7. When it is an input pin, it has an internal pull-up resistor. When it is an output pin, the sink current is 10mA and the source current is 5mA. I/O Port C6. Same as PC7. I/O Port C5. Same as PC7. I/O Port C4. Same as PC7. I/O Port C3. Same as PC7. I/O Port C2. Same as PC7. I/O Port C1 or A/D converter input 0. I/O Port C0 or A/D converter input 1. DDC serial data or I/O Port D1. When it is a DDC interface pin, It is an open- drain output. When as an I/O port, it is same as Port B. DDC serial clock or I/O Port D0. When it is a DDC interface pin, It is an open- drain output. When as an I/O port, it is same as Port B. I/O Port A0 or D/A converter 8. This pin can be the output of D/A converter 8 (source/sink = 5mA) or an I/O pin (source = -100uA, sink = 5mA). I/O Port A1 or D/A converter 9. Same as PA0/DA8. I/O Port A2 or D/A converter 10. Same as PA0/DA8. I/O Port A3 or D/A converter 11. Same as PA0/DA8. I/O Port A4 or D/A converter 12. Same as PA0/DA8. I/O Port A5 or D/A converter 13. Same as PA0/DA8. I/O Port A6 / VSYNC OUT. This pin can be the output of VSYNC or an I/O pin. When as an I/O pin, it is same as PA0. I/O Port A7 / HSYNC OUT. This pin can be the output of HSYNC or an I/O pin. When as an I/O pin, it is same as PA0. D/A converter 7. Open-drain output. External applied voltage can up to 10V. D/A converter 6. Open-drain output. External applied voltage can up to 10V. D/A converter 5. Open-drain output. External applied voltage can up to 10V. D/A converter 4. Open-drain output. External applied voltage can up to 10V. D/A converter 3. Open-drain output. External applied voltage can up to 10V. HSYNC input. Schmitt trigger input. VSYNC input. Schmitt trigger input.
1 DA2 2 DA1 3 DA0 4 /RESET/VPP 5 VDD 7 GND 8 OSCO 9 OSCI 10 PB5/SDA2 11 PB4/SCL2 12 PB3/PAT 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 38 39 40 41 42 PB2 PB1/HLFI PB0/HLFO PB6/IRQ PC7 PC6 PC5 PC4 PC3 PC2 PC1/AD1 PC0/AD0 SDA1/PD1 SCL1/PD0 PA0/DA8 PA1/DA9 PA2/DA10 PA3/DA11 PA4/DA12 PA5/DA13 PA6/VSO PA7/HSO DA7 DA6 DA5 DA4 DA3 HSYNC VSYNC
O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O I I
Weltrend Semiconductor, Inc.
2
WT60P1
Digital Monitor Controller
Ver. 1.51 Jul-31-1998
FUNCTIONAL DESCRIPTION
CPU
The CPU core is 6502 compatible, operating frequency is 4MHz. Address bus is 16-bit and data bus is 8-bit. the non-maskable interrupt (/NMI) of 6502 is changed to maskable interrupt and is defined as the INT0. The interrupt request (/IRQ) of 6502 is defined as the INT1. Default stack pointer is 01FFH. Please refer the 6502 reference menu for more detail.
ROM
16384 bytes flash memory are provided for program codes. Address is located from C000H to FFFFH. The following addresses are reserved for special purpose : FFFAH (low byte) and FFFBH (high byte) : INT0 interrupt vector. FFFCH (low byte) and FFFDH (high byte) : program reset vector. FFFEH (low byte) and FFFFH (high byte) : INT1 interrupt vector.
RAM
Built-in 288 bytes SRAM, address is located from 0080H to 019FH. Because the initial stack pointer is 01FFH, so program must set proper stack pointer when program starts. A recommended value is 019FH. Note : If user wants to emulate WT6014, please set bit 7 in REG#7FH. This will set stack pointer to 00FFH. 0000H : 0020H 0021H : 007FH 0080H : 019FH 01A0H : BFFFH C000H : : : FFFFH
REGISTERS
Reserved
RAM
Reserved
ROM
Low VDD Voltage Reset
A VDD voltage detector is built inside the chip. When VDD is below 4.0 volts, the whole chip will be reset just like power-on-reset. Note that the 4.0 volts varies with temperature and process. Please refer the electrical characteristics.
Weltrend Semiconductor, Inc.
3
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