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Details, datasheet, quote on part number:WT6132
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Datasheet text preview:
WT6132/WT6124/WT6116
Data Sheet Rev. 1.01
GENERAL DESCRIPTION
The WT6132/WT6124/WT6116 is a microcontroller for digital controlled monitor with Universal Serial Bus (USB) interface. It contains an 8-bit CPU, 32K/24K/16K bytes ROM, 512/384 bytes RAM, 14 PWMs, 2 parallel I/Os, SYNC signal processor, timer, DDC1/2B interface, master/slave I C interface, low speed USB device module, 6-bit A/D converter and watch-dog timer.
FEATURES
· 8-bit 6502 compatible CPU with 6MHz operating frequency · W T6132 - 32768 bytes ROM, 512 bytes RAM W T6124 - 24576 bytes ROM, 512 bytes RAM W T6116 - 16384 bytes ROM, 384 bytes RAM · 12MHz crystal oscillator · 14 channels 8-bit PWM outputs · Sync signal processor with H+V separation, H/V frequency counter, H/V polarity detection/control and clamp pulse output · Six free-running sync signal outputs (Horizontal frequency up to 106KHz) · Self-test pattern · DDC1/2B supported 2 · Fast mode master/slave I C interface (up to 400KHz) · Watch-dog timer · Maximum 28 programmable I/O pins · One 8-bit programmable timer · 6-bit A/D converter with 4 selectable inputs · One external interrupt request input · Low VDD reset
PIN CONFIGURATION
DIP 40-pin
PW M2 PW M1 PW M0 RESET VDD GND OSCO OSCI PB5/SDA2 PB4/SCL2 PB3/PAT PB2 PB1/HFI PB0/HFO IRQ PC7/SOGIN PC6 PC5 PC4 PC3/AD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VIN HIN PW M3 PD5/PW M4 PD4/PW M5 PD3/PW M6 PD2/PW M7 PD1/HOUT PD0/VOUT PA7/PW M13/CLAMP PA6/PW M12 PA5/PW M11 PA4/PW M10 PA3/PW M9 PA2/PW M8 PA1/SCL1 PA0/SDA1 PC0/AD0 PC1/AD1 PC2/AD2 PW M2 PW M1 PW M0 RESET VDD GND OSCO OSCI PB5/SDA2 PB4/SCL2 PB3/PAT PB2 PB1/HFI PB0/HFO IRQ PC7/SOGIN PC6 PC5 PC4 PC3/AD3
Shrink DIP 42-pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VIN HIN PW M3 PD5/PW M4 PD4/PW M5 PD3/PW M6 PD2/PW M7 PD1/HOUT PD0/VOUT PA7/PW M13/CLAMP PA6/PW M12 PA5/PW M11 PA4/PW M10 PA3/PW M9 PA2/PW M8 PA1/SCL1 PA0/SDA1 PC0/AD0 PC1/AD1 PC2/AD2
W T 6132 W T 6124 W T 6116
W T 6132 W T 6124 W T 6116
Weltrend Semiconductor, Inc.
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WT6132/WT6124/WT6116
Data Sheet Rev. 1.01 PIN DESCRIPTION
Pin No. 42 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name NC PW M2 PW M1 PW M0 /RESET VDD G ND OSCO OSCI PB5/ SDA2 PB4/ SCL2 PB3/PAT PB2 PB1/HFI PB0/HFO /IRQ PC7/SOGIN PC6 PC5 PC4 PC3/AD3 PC2/AD2 PC1/AD1 PC0/AD0 PA0/SDA1 PA1/SCL1 PA2/PW M8 PA3/PW M9 PA4/PW M10 PA5/PW M11 PA6/PW M12 PA7/PW M13/ CLAMP PD0/VOUT PD1/HOUT PD2/PW M7 PD3/PW M6 PD4/PW M5 PD5/PW M4 PW M3 HIN VIN NC I/O O O O I Description No connection. PW M2 output (10V open-drain). PW M1 output (5V open-drain). PW M0 output (5V open-drain). Reset input. +5V power supply. Ground. 12MHz oscillator output. 12MHz oscillator input. 2 Port B5 or I C interface data line. 2 Port B4 or I C interface clock line. Port B3 or test pattern output Port B2. Port B1 or half frequency divider input. Port B0 or half frequency divider output. Interrupt request input, A low level on this can generate interrupt. Port C7 or Sync on Green input. Port C6. Port C5. Port C4. Port C3 or ADC input 3. Port C2 or ADC input 2. Port C1 or ADC input 1. Port C0 or ADC input 0. Port A0 or DDC interface SDA pin. Port A1 or DDC interface SCL pin. Port A2 or PWM8 output. Port A3 or PWM9 output. Port A4 or PWM10 output. Port A5 or PWM11 output. Port A6 or PWM12 output. Port A7 or PWM13 output or clamp pulse output. Port D0 or Vsync output. Port D1 or Hsync output. Port D2 or PWM7 output. Port D3 or PWM6 output. Port D4 or PWM5 output. Port D5 or PWM4 output. PW M3 output (10V open-drain). Hsync Input. Vsync input. No connection.
I/O I I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I
Weltrend Semiconductor, Inc.
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WT6132/WT6124/WT6116
Data Sheet Rev. 1.01
FUNCTIONAL DESCRIPTION
CPU
8-bit 6502 compatible CPU operates at 6MHz. Address bus is 16-bit and data bus is 8-bit. The non-maskable interrupt (/NMI) of 6502 is modified to be maskable and is defined as INT0 with higher priority. The interrupt request (/IRQ) of 6502 is defined as INT1 with lower priority. Please refer the 6502 reference menu for more detail.
RAM
W T6132 and WT6124 have 512 bytes RAM. Address is located from $0080h to $00FFh and $0180h to $02FFh. W T6116 have 384 bytes RAM. Address is located from $0080h to $00FFh and $0180h to $027Fh.
ROM
For WT6132, ROM is located from $8000h to $FFFFh. For WT6124, ROM is located from $A000h to $FFFFh. For WT6116, ROM is located from $C000h to $FFFFh. The following addresses are reserved for special purpose : $FFFAh (low byte) and $FFFBh (high byte) : INT0 interrupt vector. $FFFCh (low byte) and $FFFDh (high byte) : program reset interrupt vector. $FFFEh (low byte) and $FFFFh (high byte) : INT1 interrupt vector. $0000h : $003Fh $0040h : $007Fh $0080h : $00FFh $0100h : $017Fh $0180h : $02FFh $0300h : $0FFFh $1000h : $7FFFh $8000h : : : $FFFFh Registers Reserved 128 bytes RAM Reserved 384 bytes RAM Reserved Reserved
ROM
Weltrend Semiconductor, Inc.
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