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Details, datasheet, quote on part number:68020
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| Part: | 68020 |
| Category: | Microprocessors => 68000 Processors |
| Description: | Part Number = WC32P020-XQ2M ;; Speed MHZ = 16,20,25 ;; Package = 132 CQFP ;; Temp = M ;; |
| Company: | White Electronic Designs Corporation |
| Datasheet: | Download 68020 datasheet File size : 259 kB |
| Request For quote: | Find where to buy 68020
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Datasheet text preview:
WC32P020-XXM
68020 FEATURES
s Selection of Processor Speeds: 16.67, 20, 25 MHz s Military Temperature Range: -55°C to +125°C s Packaging · 114 pin Ceramic PGA (P2) · 132 lead Ceramic Quad Flatpack, CQFP (Q2) s Object-code compatible with earlier 68000 Microprocessors s Addressing mode extensions for enhanced support of highlevel languages s Bit Field Data Type Accelerates Bit-Oriented Applications i.e., Video Graphics s Fast On-Chip Instruction Cache Speeds Instructions and Improves Bus Bandwidth s Coprocessor Interface to Companion 32-Bit Peripheralsthe 68881 and 68882 Floating-Point Coprocessors and the 68851 Paged Memory Management Unit s Pipelined Architecture with High Degree of Internal Parallelism allowing Multiple Instructions to be executed concurrently s High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32-Bits s Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peripherals s Full Support of Virtual Memory and Virtual Machine s 16 32-Bit General-Purpose Data and Address Registers s Two 32-Bit Supervisor Stack Pointers and Five SpecialPurpose Control Registers s 18 Addressing Modes and 7 Data Types s 4 GigaByte Direct Addressing Range
DESCRIPTION
The WC32P020 is a 32-bit implementation of the 68000 Family of microprocessors. Using HCMOS technology, the WC32P020 is implemented with 32-bit registers and data paths, 32-bit addresses, a powerful instruction set, and flexible addressing modes.
FIG. 1
BLOCK DIAGRAM
December 1998
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White Microelectronics · Phoenix, AZ · (602) 437-1520
WC32P020-XXM
FIG. 2
PIN CONFIGURATION FOR WC32P020-XXM, CQFP (Q2) TOP VIEW
NC NC GND BG VDD GND GND CLK RESET VDD VDD RMC FC0 FC1 FC2 SIZ0 SIZ1 DBEN ECS CDIS AVEC DSACK0 DSACK1 BERR GND GND HALT AS DS GND GND R/W NC
NC BGAC BR A0 A1 A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 VDD VDD GND GND A16 A15 A14 A13 A12 A11 A10 NC NC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
NC D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 GND GND VDD VDD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 NC NC
FIG. 3
PIN CONFIGURATION FOR WC32P020-XXM, PGA (P2)
N D31 M DS L AS K GND HALT GND J DSACK1 BERR GND H CDIS AVEC DSACK0 G ECS SIZ1 DBEN F SIZ0 E FC0 RMC D VCC C RESET CLK GND B GND A BGACK A1 1 2 A31 3 A28 4 A26 5 A23 6 A22 7 A19 8 VCC 9 GND 10 A14 11 A11 12 A8 13 BG BR A30 A27 A24 A20 A18 GND D15 D13 A10 A6 A0 A29 A25 A21 A17 A16 A12 A9 A7 A5 VCC VCC A4 A3 VCC A2 OCS FC2 FC1 GND IPEND VCC GND VCC IPL2 GND IPL0 IPL1 D1 D0 R/W D30 D27 D23 D19 GND D15 D11 D7 GND D3 D2 D29 D26 D24 D21 D18 D16 VCC D13 D10 D6 D5 D4 D28 D25 D22 D20 D17 GND VCC D14 D12 D9 D8 VCC
White Microelectronics · Phoenix, AZ · (602) 437-1520
NC NC NC A9 A8 A7 A6 A5 A4 A3 A2 GND OSC IPEND VDD VDD GND GND IPL2 IPL1 IPL0 D0 D1 D2 D3 D4 GND GND VDD VDD D5 NC NC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
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WC32P020-XXM
ADDRESSING MODES
Addressing Register Direct Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Register Indirect with Index Address Register Indirect with Index (8-Bit Displacement) Address Register Indirect with Index (Base Displacement) Memory Indirect Memory Indirect Postindexed Memory Indirect Preindexed Program Counter Indirect with Displacement Program Counter Indirect with Index PC Indirect with Index (8-Bit Displacement) PC Indirect with Index (Base Displacement) Program Counter Memory Indirect PC Memory Indirect Postindexed PC Memory Indirect Preindexed Absolute Absolute Short Absolute Long Immediate Syntax Dn An (An) (An) + - (An) (d16,An) (d8,An,Xn) (bd,An,Xn) ([bd,An],Xn,od) ([bd,An,Xn],od) (d16,PC) (d8,PC,Xn) (bd,PC,Xn) ([bd,PC],Xn,od) ([bd,PC,Xn],od) (xxx).W (xxx).L #(data) Mnemonic Bcc BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BRA BSET BSR BTST CALLM CAS CAS2 CHK CHK2 CLR CMP CMPA CMPI CMPM CMP2 DBcc DIVS, DIVSL DIVU, DIVUL EOR EORI EXG EXT, EXTB ILLEGAL JMP JSR LEA LINK LSL, LSR MOVE MOVEA MOVE CCR MOVE SR MOVE USP MOVEC MOVEM MOVEP MOVEQ MOVES MULS MULU Description Branch Conditionally Test Bit and Change Test Bit and Clear Test Bit Field and Change Test Bit Field and Clear Signed Bit Field Extract Unsigned Bit Field Extract Bit Field Find First One Bit Field Insert Test Bit Field and Set Test Bit Field Breakpoint Branch Test Bit and Set Branch to Subroutine Test Bit Call Module Compare and Swap Operands Compare and Swap Dual Operands Check Register Against Bound Check Register Against Upper and Lower Bounds Clear Compare Compare Address Compare Immediate Compare Memory to Memory Compare Register Against Upper and Lower Bounds Test Condition, Decrement and Branch Signed Divide Unsigned Divide Logical Exclusive OR Logical Exclusive OR Immediate Exchange Registers Sign Extend Take Illegal Instruction Trap Jump Jump to Subroutine Load Effective Address Link and Allocate Logical Shift Left and Right Move Move Address Move Condition Code Register Move Status Register Move User Stack Pointer Move Control Register Move Multiple Registers Move Peripheral Move Quick Move Alternate Address Space Signed Multiply Unsigned Multiple
NOTES: Dn = Data Register, DO-D7 An = Address Register, AO-A7 d8, d16 = A twos-complement or sign-extended displacement; added as part of the effective address calculation; size is 8 (d8) or 16 (d16) bits; when omitted, assemblers use a value of zero. Xn = Address or data register used as an index register; form is Xn.SIZE*SCALE, where SIZE is.W or .L (indicates index register size) and SCALE is 1, 2, 4, or 8 (index register is multiplied by SCALE); use of SIZE and/or SCALE is optional. bd = A twos-complement base displacement; when present, size can be 16 or 32 bits. od = 0uter displacement, added as part of effective address calculation after any memory indirection, use is optional with a size of 16 or 32 bits. PC = Program Counter (data) = Immediate value of 8, 16, or 32 bits ( ) = Effective Address [ ] = Use as indirect access to long-word address.
INSTRUCTION SET
Mnemonic ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ASL, ASR Description Add Decimal with Extend Add Add Address Add Immediate Add Quick Add with Extend Logical AND Logical AND Immediate Arithmetic Shift Left and Right
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White Microelectronics · Phoenix, AZ · (602) 437-1520
WC32P020-XXM
INSTRUCTION SET (cont.)
Mnemonic NBCD NEG NEGX NOP NOT OR ORI ORI CCR ORI SR PACK PEA RESET ROL, ROR ROXL, ROXR RTD RTE RTM RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPcc TRAPV TST UNLK UNPK Description Negate Decimal with Extend Negate Negate with Extend No Operation Logical Complement Logical Inclusive OR Logical Inclusive OR Immediate Logical Inclusive OR Immediate to Condition Codes Logical Inclusive OR Immediate to Status Register Pack BCD Push Effective Address Reset External Devices Rotate Left and Right Rotate with Extend Left and Right Return and Deallocate Return from Exception Return from Module Return and Restore Codes Return from Subroutine Subtract Decimal with Extend Set Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract with Extend Swap Register Words Test Operand and Set Trap Trap Conditionally Trap on Overflow Test Operand Unlink Unpack BCD
SIGNAL DESCRIPTION
The Vcc and GND pins are separated into four groups to provide individual power supply connections for the address bus buffers, data bus buffers, and all other buffers and internal logic. See Fig. 4.
Group Address Bus Data Bus Logic Clock Vcc A9, D3 M8, N8, N13 D1, D2, E3, G11, G13 -- GND A10, B9, C3, F12 L7, L11, N7, K3 G12, H13, J3, K1 B1
FIG. 4
FUNCTIONAL SIGNAL GROUPS
FUNCTION CODES ADDRESS BUS DATA BUS
FC0-FC2 A0-A31 D0-D31
CDIS INTERRUPT PRIORITY
CACHE CONTROL
IPL0-IPL2 IPEND AVEC SIZ0 SIZ1 INTERRUPT CONTROL
TRANSFER SIZE
BR BG BGACK RESET HALT BERR CLK Vcc (10) GND (13)
BUS ARBITRATION CONTROL
ASYNCHRONOUS BUS CONTROL
ECS OCS RMC AS DS R/W DBEN DSACK0 DSACK1
BUS EXCEPTION CONTROL
Coprocessor Instructions
Mnemonic cpBcc cpDBcc cpGEN Mnemonic cpRESTORE cpSAVE cpScc cpTRAPcc Description Branch Conditionally Test Coprocessor Condition, Decrement and Branch Coprocessor General Instruction Description Restore Internal State of Coprocessor Save Internal State of Coprocessor Set Conditionally Trap Conditionally
White Microelectronics · Phoenix, AZ · (602) 437-1520
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WC32P020-XXM
SIGNAL INDEX
Signal Name Function Codes Address Bus Data Bus Size External Cycle Start Operand Cycle Start Read,Write Read-Modify-Write Cycle Address Strobe Data Strobe Data Buffer Enable Data Transfer and Size Acknowledge Interrupt Priority Level Interrupt Pending Autovector Bus Request Bus Grant Bus Grant Acknowledge Reset Halt Bus Error Cache Disable Clock Power Supply Ground Mnemonic FC2-FC0 A0-A31 D0-D31 SIZ0/SIZ1 ECS OCS R/W RMC AS DS DBEN DSACK0/DSACK1 32-bit address bus. 32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus cycle. Indicates the number of bytes remaining to be transferred for this cycle. These signals, together with A1 and A0, define the active sections of the data bus. Provides an indication that a bus cycle is beginning. Identical operation to that of ECS except that OCS is asserted only during the first bus cycle of an operand transfer. Defines the bus transfer as a processor read or write. Provides an indicator that the current bus cycle is part of an indivisible read-modify-write operation. Indicates that a valid address is on the bus. Indicates that valid data is to be placed on the data bus by an external device or has been placed on the data bus by the WC32P020-XXM. Provides an enable signal for external data buffers. Bus response signals that indicate the requested data transfer operation has completed. In addition, these two lines indicate the size of the external bus port on a cycle-by-cycle basis and are used for asynchronous transfers. Provides an encoded interrupt level to the processor. Indicates that an interrupt is pending. Requests an autovector during an interrupt acknowledge cycle. Indicates that an external device requires bus mastership. Indicates that an external device may assume bus mastership. Indicates that an external device has assumed bus mastership. System reset. Indicates that the processor should suspend bus activity. Indicates that an erroneous bus operation is being attempted. Dynamically disables the on-chip cache to assist emulator support Clock input to the processor. Power supply. Ground connection. Function 3-bit function code used to identify the address space of each bus cycle.
IPL0-IPL2 IPEND AVEC BR BG BGACK RESET HALT BERR CDIS CLK Vcc GND
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White Microelectronics · Phoenix, AZ · (602) 437-1520
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