|
|
Part: EDI2AG272129V-10
Category:
Memory
-> SRAM
-> Modules->SSRAM->SSRAM Modules
Description: Organization = 2x128Kx72 ;; Speed (ns) = 9-12 ;; Volt = 3.3 ;; Package = 144 So-dimm ;; Temp = C ;;
Company: White Electronic Designs Corporation
Datasheet: Download EDI2AG272129V-10 datasheet File size : 825 kB
Request For quote: Find where to buy EDI2AG272129V-10
Datasheet text preview:
EDI2AG272129V
2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM
FEATURES
s 2x128Kx72 Synchronous, Synchronous Burst s Access Speed(s): TKHQV = 8.5, 9, 10, 12ns s Flow-Through Architecture s Sequential Burst Mode s Clock Controlled Registered Bank Enables (E1\, E2\) s Clock Controlled Byte Write Mode Enable (BWE\) s Clock Controlled Byte Write Enables (BW1\ - BW8\) s Clock Controlled Registered Address s Clock Controlled Registered Global Write (GW\) s Aysnchronous Output Enable (G\) s Internally self-timed Write s Gold Lead Finish s 3.3V ±10% Operation s Common Data I/O s High Capacitance (30pF) drive, at rated Access Speed s Single total array Clock s Multiple Vcc and Vss
ADVANCED*
The EDI2AG272129VxxD1 is a Synchronous/Synchronous Burst SRAM, 72 position DIMM (144 contacts) Module, organized as 2x128Kx72. The Module contains four (4) Synchronous Burst R a m Devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The module architecture is defined as a Sync/Sync Burst, FlowThrough, with support for linear burst. This module provides High Performance, 2-1-1-1 accesses when used in Burst Mode, and used as a Synchronous Only Mode, provides a high performance cost advantage over BiCMOS aysnchronous device architectures. Synchronous Only operations are performed via strapping ADSC\ Low, and ADSP\ / ADV\ High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes. Synchronous/Synchronous Burst operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output enable. This Module has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as Quad Words in both Read and Write Operations.
* This data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice.
July 1998 Rev. ECO#
1
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
EDI2AG272129V
PIN CONFIGURATION PIN SYMBOLS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 FUNCTION VSS VSS A0 RFU A16 A1 A2 A15 A14 A3 A4 A13 A12 A5 A6 A11 A10 A7 A8 A9 VCC VCC G\ RFU GW\ ADV\ ADSP\ ADSC\ E1\ CLK E2\ BWE\ BW1\ DQP0 VCC VCC PIN 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 FUNCTION DQ0 DQ7 DQ1 DQ6 DQ2 DQ5 DQ3 DQ4 VSS VSS BW2\ DQP1 VCC VCC DQ8 DQ15 DQ9 DQ14 DQ10 DQ13 DQ11 DQ12 VSS VSS BW3\ DQP2 VCC VCC DQ16 DQ23 DQ17 DQ22 DQ18 DQ21 DQ19 DQ20 PIN 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 FUNCTION VSS VSS BW4\ DQP3 VCC VCC DQ24 DQ31 DQ25 DQ30 DQ26 DQ29 DQ27 DQ28 VSS VSS BW5\ DQP4 VCC VCC DQ32 DQ39 DQ33 DQ38 DQ34 DQ37 DQ35 DQ36 VSS VSS BW6\ DQP5 VCC VCC DQ40 DQ47 PIN 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 FUNCTION DQ41 DQ46 DQ42 DQ45 DQ43 DQ44 VSS VSS BW7\ DQP6 VCC VCC DQ48 DQ55 DQ49 DQ54 DQ50 DQ53 DQ51 DQ52 VSS VSS BW8\ DQP7 VCC VCC DQ56 DQ63 DQ57 DQ62 DQ58 DQ61 DQ59 DQ60 VSS VSS
ADSC\ ADSP\ ADV\ BWE\ CLK G\ GW\ E\ BW\
PIN NAMES
DQ0-63 DQP0-7 A 0-16 E1, E2\ BWE\ BW1-8\ CLK GW\ G\ Vcc Vss Input/Output Bus Parity Bits Address Bus Synchronous Bank Enables Byte Write Mode Enable Byte Write Enables Array Clock Synchronous Global Write Enable Asynchronous Output Enable 3.3V Power Supply Ground
FUNCTIONAL BLOCK DIAGRAM
A0-16 ADSC\ ADSP\ ADV\ BWE\ CLK G\ GW\
E1\ BW1-4\
ADSC\ ADSP\ ADV\ BWE\ CLK G\ GW\ E\ BW\
DQ
DQ0-31 DQP0-3
U1
E2\
ADSC\ ADSP\ ADV\ BWE\ CLK G\ GW\ E\ BW\
DQ
DQ0-31 DQP0-3
U2
DQ
DQ32-63 DQP4-7
BW5-8\
U3
ADSC\ ADSP\ ADV\ BWE\ CLK G\ GW\ E\ BW\
DQ
DQ32-63 DQP4-7
U4
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
2
EDI2AG272129V
PIN DESCRIPTIONS
DIMM Pins 3, 6, 7, 10, 11, 14 15, 18, 19, 20, 17 16, 13, 12, 9, 8, 5 33, 47, 61, 75, 89, 103, 117, 131 32 25 30 29, 31 23 26 27 28 Various 34, 48, 62, 76, 90, 104, 118, 132 Various Various Symbol A0-16 Type Input Synchronous Input Synchronous Description Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle. Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW0/ controls DQ0-7 and DQP0, BW1\ controls DQ8-15 and DQP1. BW2\ controls DQ16-23 and DQP2. BW3\ controls DQ24-31 and DQP3. BW4\ controls DQ32-39 and DQP4. BW5\ controls DQ40-47 and DQP5. BW6\ controls DQ48-55 and DQP6. BW7\ controls DQ56-64 and DQP7. Write Enable: This active LOW input gates byte write operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and BWx\ lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP\. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Status Processor: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with EL\ and EH\ being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64. Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15. DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4\ is parity bit for DQ32-39. DQP5 is parity bit for DQ40-47. DQP6\ is parity bit for DQ48-55. DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device configured as a 128K x 64, the parity bits need to be tied to Vss through a 10K ohm resistor. Core power supply: +3.3V -5%/+10% Ground
BW1\, BW2\, BW3\, BW4\, BW5\, BW6\, BW7\, BW8\ BWE\ GW\ CLK E1\, E2\ G\ ADV\ ADSP\ ADSC\ DQ0-63 DQP0-7
Input Synchronous Input Synchronous Input Synchronous Input Synchronous Input Input Synchronous Input Synchronous Input Synchronous Input/Output Input/Output
Vcc Vss
Supply Ground
3
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
EDI2AG272129V
SYNCHRONOUS BURST - TRUTH TABLE
Operation Deselected Cycle, Power Down; Bank 1 Deselected Cycle, Power Down; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 2 Write Cycle, Begin Burst; Bank 1 Write Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 2 E1\ H X L L H H L H L L H H X X H H H H H H X H H H X X H H H H H H X H H H E2\ X H H H L L H L H H L L H H X X H H H H H H X H H H X X H H H H H H X H ADSP\ X X L L L L H H H H H H X X X X X X X X H X H X H H H H X X X X H X H X ADSC\ L L X X X X L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H ADV\ X X X X X X X X X X X X L L L L L L L L L L L L H H H H H H H H H H H H GW\ X X X X X X L L H H H H H H H H H H H H L L L L H H H H H H H H L L L L G\ X X L H L H X X L H L H L H L H L H L H X X X X L H L H L H L H X X X X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z D D D D Q High-Z Q High-Z Q High-Z Q High-Z D D D D Addr. Used None None External External External External External External External External External External Next Next Next Next Next Next Next Next Next Next Next Next Current Current Current Current Current Current Current Current Current Current Current Current
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
4
EDI2AG272129V
SYNCHRONOUS ONLY - TRUTH TABLE
Operation Synchronous Write-Bank 1 Synchronous Read-Bank 1 Synchronous Write-Bank 2 Synchronous Read-Bank 2 E1\ L L H H E2\ H H L L GW\ L H L H G\ H L H L ZZ L L L L CLK DQ High-Z High-Z
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Relative to Vss Vin Storage Temperature Operating Temperature (Commercial) Operating Temperature (Industrial) Short Circuit Output Current -0.5V to +4.6V -0.5V to Vcc +0.5V -55°C to +125°C 0°C to +70°C -40°C to +85°C 10 mA
RECOMMENDED DC OPERATING CONDITIONS
Parameter Supply Voltage Supply Voltage Input High Input Low Input Leakage Output Leakage Sym VCC VSS VIH VIL ILI ILo Min 3.14 0.0 2.2 -0.3 -2 -2 Typ 3.3 0.0 3.0 0.0 1 1 Max 3.6 0.0 VCC +0.3 0.3 2 2 Units V V V V µA µA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Max Description Power Supply Current Power Supply Current
Device Selected,No Operation
Symbol Icc1 Icc Icc3 IccK
Typ 1.6 750 250 600
8.5 2.2 1.5 300 1000
9 2.1 1.5 300 1000
10 2.1 1.0 300 750
12 2.0 1.0 300 750
Units A A mA mA
CMOS Standby Clock Running-Deselect
BURST ADDRESS TABLE (MODE = NC/VCC)
First Address (external) A..A00 A..A01 A..A10 A..A11 Second Address (internal) A..A01 A..A00 A..A11 A..A10 Third Address (internal) A..A10 A..A11 A..A00 A..A01 Fourth Address (internal) A..A11 A..A10 A..A01 A..A00
BURST ADDRESS TABLE (MODE = VSS)
First Address (external) A..A00 A..A01 A..A10 A..A11 Second Address (internal) A..A01 A..A10 A..A11 A..A00 Third Address (internal) A..A10 A..A11 A..A00 A..A01 Fourth Address (internal) A..A11 A..A00 A..A01 A..A10
AC TEST CIRCUIT
Parameter
AC TEST CONDITIONS
I/O VSS to 3.0 1.25 See figure, at left Unit V V
Output
ZZ0 = 50 0 = 50
50
Input Pulse Levels Input and Output Timing Levels Output Test Equivalencies
Vt = 1.5VV 1.25
A C Output Load Equivalent
5
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
Others parts begin by ed
ED-1 ED-2 ED-3 ED-4 ED-5 ED-6
|
|
|
