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Part: EDI2CG272128V
Category:
Memory
-> SRAM
-> Modules->SSRAM->SSRAM Modules
Description: Organization = 2x128Kx72 ;; Speed (ns) = 9-12 ;; Volt = 3.3 ;; Package = 144 So-dimm ;; Temp = C ;;
Company: White Electronic Designs Corporation
Datasheet: Download EDI2CG272128V datasheet File size : 825 kB
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Datasheet text preview:
EDI2CG272128V
2x128Kx72, 3.3V Sync/Sync Burst Flow-Through
FEATURES
s 2x128Kx72 Synchronous, Synchronous Burst s Flow-Through Architecture s Linear and Sequential Burst Support via MODE pin s Access Speed(s): TKHQV = 8.5, 9, 12, 15ns s Clock Controlled Registered Bank Enables (E1, E2) s Clock Controlled Registered Address s Clock Controlled Registered Global Write (GW) s Aysnchronous Output Enable (G) s Internally Self-timed Write s Individual Bank Sleep Mode Enables (ZZ1, ZZ2) s Gold Lead Finish s 3.3V ±10% Operation s Common Data I/O s High Capacitance (30pF) Drive, at Rated Access Speed s Single Total Array Clock s Multiple Vcc and Gnd The EDI2CG272128VxxD1 is a Synchronous/Synchronous Burst SRAM, 72 position DIMM (144 contacts) Module, small outline. The Module contains four (4) Synchronous Burst Ram Devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The module architecture is defined as a Sync/Sync Burst, Flow-Through, with support for either linear or sequential burst. This module provides High Performance, 2-1-1-1 accesses when used in Burst Mode, and used as a Synchronous Only Mode, provides a high performance cost advantage over BiCMOS aysnchronous device architectures. Synchronous Only operations are performed via strapping ADSC Low, and ADSP / ADV High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes. Synchronous/Synchronous Burst operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output enable. This Module has been defined for Quad Word access in both read and write operations.
August 2000 Rev.0 ECO#13088
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White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
EDI2CG272128V
PIN CONFIGURATION PIN SYMBOLS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 FUNCTION VSS VSS A0 RFU A16 A1 A2 A15 A14 A3 A4 A13 A12 A5 A6 A11 A10 A7 A8 A9 VCC VCC G RFU GW ADV ADSP ADSC MODE CLK VSS VSS E1 DQP0 VCC VCC PIN 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 FUNCTION DQ0 DQ7 DQ1 DQ6 DQ2 DQ5 DQ3 DQ4 VSS VSS ZZ1 DQP1 VCC VCC DQ8 DQ15 DQ9 DQ14 DQ10 DQ13 DQ11 DQ12 VSS VSS E2 DQP2 VCC VCC DQ16 DQ23 DQ17 DQ22 DQ18 DQ21 DQ19 DQ20 PIN 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 FUNCTION VSS VSS ZZ2 DQP3 VCC VCC DQ24 DQ31 DQ25 DQ30 DQ26 DQ29 DQ27 DQ28 VSS VSS RFU DQP4 VCC VCC DQ32 DQ39 DQ33 DQ38 DQ34 DQ37 DQ35 DQ36 VSS VSS RFU DQP5 VCC VCC DQ40 DQ47 PIN 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 FUNCTION DQ41 DQ46 DQ42 DQ45 DQ43 DQ44 VSS VSS RFU DQP6 VCC VCC DQ48 DQ55 DQ49 DQ54 DQ50 DQ53 DQ51 DQ52 VSS VSS RFU DQP7 VCC VCC DQ56 DQ63 DQ57 DQ62 DQ58 DQ61 DQ59 DQ60 VSS VSS
E2
ADSC ADSP ADV CLK G GW E ZZ
PIN NAMES
DQ0-63 DQP0-7 A 0-16 E1, E2 CLK GW G Input/Output Bus Parity Bits Address Bus Synchronous Bank Enables Array Clock Synchronous Global Write Enable Asynchronous Output Enable
ZZ1, ZZ2 Blank Sleep Mode Enables Vcc Vss NC 3.3V Power Supply Ground No Connect
FIG. 1
A0-16 ADSC ADSP ADV CLK G GW
FUNCTIONAL BLOCK DIAGRAM
E1 ZZ1
ADSC ADSP ADV CLK G GW E ZZ
DQ
DQ0-31 DQP0-3
U1
DQ
DQ0-31 DQP0-3
U2
ZZ2
ADSC ADSP ADV CLK G GW E ZZ
DQ
DQ32-63 DQP4-7
U3
ADSC ADSP ADV CLK G GW E ZZ
DQ
DQ32-63 DQP4-7
U4
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
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August 2000 Rev.0 ECO#13088
EDI2CG272128V
PIN DESCRIPTIONS
DIMM Pins 3, 6, 10, 11, 14, 15, 18, 19, 20, 17, 16, 13, 12, 9, 8, 3, 5 25 30 33, 61 23 26 27 28 29 47, 75 Various 34, 48, 62, 76, 90, 104, 118, 132 Symbol A0-16 Type Input Synchronous Input Synchronous Input Synchronous Input Synchronous Input Input Synchronous Input Synchronous Input Synchronous Input Static Input Asynchronous Input/Output Input/Output Description Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle. Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE and BWx lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP Output Enable: This active LOW asynchronous input enables the data output drivers. Address Status Processor: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with EL and EH being LOW, causes a new externaladdress to be registered and a READ cycle is initiated using the new address. Address Status Controller: This active LOW input causes device to be de-selected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Snooze: These active HIGH inputs put the individual banks in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (no connect). Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64. Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15. DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4 is parity bit for DQ32-39. DQP5 is parity bit for DQ40-47. DQP6 is parity bit for DQ48-55. DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device configured as a 128K x 64, the parity bits need to be tied to Vss through a 10K ohm resistor. Core power supply: +3.3V -5%/+10% Ground
GW CLK E1, E2 G ADV ADSP ADSC MODE ZZ1, ZZ2 DQ0-63 DQP0-7
Various Various
Vcc Vss
Supply Ground
August 2000 Rev.0 ECO#13088
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White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
EDI2CG272128V
SYNCHRONOUS BURST - TRUTH TABLE
Operation Deselected Cycle, Power Down; Bank 1 Deselected Cycle, Power Down; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 2 Write Cycle, Begin Burst; Bank 1 Write Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 2 E1 H X L L H H L H L L H H X X H H H H H H X H H H X X H H H H H H X H H H E2 X H H H L L H L H H L L H H X X H H H H H H X H H H X X H H H H H H X H ADSP X X L L L L H H H H H H X X X X X X X X H X H X H H H H X X X X H X H X ADSC L L X X X X L L L L L L H H H H H H H H H H H H H H H H H H H H H H H H ADV X X X X X X X X X X X X L L L L L L L L L L L L H H H H H H H H H H H H GW X X X X X X L L H H H H H H H H H H H H L L L L H H H H H H H H L L L L G X X L H L H X X L H L H L H L H L H L H X X X X L H L H L H L H X X X X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z D D D D Q High-Z Q High-Z Q High-Z Q High-Z D D D D Addr. Used None None External External External External External External External External External External Next Next Next Next Next Next Next Next Next Next Next Next Current Current Current Current Current Current Current Current Current Current Current Current
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
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August 2000 Rev.0 ECO#13088
EDI2CG272128V
SYNCHRONOUS ONLY - TRUTH TABLE
Operation Synchronous Write-Bank 1 Synchronous Read-Bank 1 Synchronous Write-Bank 2 Synchronous Read-Bank 2 Synchronous Write-Bank 3 Synchronous Read-Bank 3 Synchronous Write-Bank 4 Synchronous Read-Bank 4 Snooze Mode E1 L L H H H H H H X E2 H H L L H H H H X GW L H L H L H L H X G H L H L H L H L X ZZ L L L L L L L L H CLK X DQ High-Z High-Z High-Z High-Z High-Z
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Relative to Vss Vin Storage Temperature Operating Temperature (Commercial) Operating Temperature (Industrial) Short Circuit Output Current -0.5V to +4.6V -0.5V to Vcc +0.5V -55°C to +125°C 0°C to +70°C -40°C to +85°C 10 mA
RECOMMENDED DC OPERATING CONDITIONS
Parameter Supply Voltage Supply Voltage Input High Input Low Input Leakage Output Leakage Sym VCC VSS VIH VIL ILI ILo Min 3.14 0.0 2.0 -0.3 -2 -2 Typ 3.3 0.0 3.0 0.0 1 1 Max 3.6 0.0 VCC +0.3 0.8 2 2 Units V V V V µA µA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Max Description Power Supply Current Power Supply Current
Device Selected, No Operation
Symbol Icc1 Icc IccZZ Icc3 IccK
Typ 1.55 750 150 400 600
8.5 2.2 1.5 200 600 1.0
9 2.1 1.5 200 600 1.0
12 2.1 1.0 200 600 0.75
15 2.0 1.0 200 600 0.75
Units A A mA mA A
Snooze Mode CMOS Standby Clock Running-Deselect
AC TEST CIRCUIT
Parameter
AC TEST CONDITIONS
I/O VSS to 3.0 1.25 See figure, at left Unit V V
I/O
Z00 = 50 Z = 50
50
Input Pulse Levels Input and Output Timing Levels Output Test Equivalencies
Vt = 1.5VV 1.25
FIG. 2
AC OUTPUT LOAD EQUIVALENT
August 2000 Rev.0 ECO#13088
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White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
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