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Part: EDI2CG472256V-15
Category:
Memory
-> SRAM
-> Modules->SSRAM->SSRAM Modules
Description: Organization = 4x256Kx72 ;; Speed (ns) = 9-12 ;; Volt = 3.3 ;; Package = 168 Dimm ;; Temp = C ;;
Company: White Electronic Designs Corporation
Datasheet: Download EDI2CG472256V-15 datasheet File size : 825 kB
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Datasheet text preview:
EDI2CG472256V
4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through
FEATURES
s 4x256Kx72 Synchronous, Synchronous Burst s Flow-Through Architecture s Linear and Sequential Burst Support via MODE pin s Clock Controlled Registered Module Enable (EM\) s Clock Controlled Registered Bank Enables (E1\, E2\, E3\, E4\) s Clock Controlled Byte Write Mode Enable (BWE\) s Clock Controlled Byte Write Enables (BW1\ - BW8\) s Clock Controlled Registered Address s Clock Controlled Registered Global Write (GW\) s Aysnchronous Output Enable (G\) s Internally self-timed Write s Individual Bank Sleep Mode enables (ZZ1, ZZ2, ZZ3, ZZ4) s Gold Lead Finish s 3.3V ±10%, - 5% Operation s Access Speed(s): tKHQV = 9, 10, 12, 15ns s Common Data I/O s High Capacitance (30pF) drive, at rated Access Speed s Single total array Clock s Multiple Vcc and Gnd The EDI2CG472256VxxD2 is a Synchronous/Synchronous Burst SRAM, 84 position Dual Key; Double High DIMM (168 contacts) Module, organized as 4x256Kx72. The Module contains sixteen (16) Synchronous Burst Ram Devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The module architecture is defined as a Sync/Sync Burst, Flow-Through, with support for either linear or sequential burst. This module provides High Performance, 2-1-1-1 accesses when used in Burst Mode, and used as a Synchronous Only Mode, p ro vi d e s a high performance cost advantage over BiCMOS aysnchronous device architectures. Synchronous Only operations are performed via strapping ADSC\ Low, and ADSP\ / ADV\ High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes. Synchronous/Synchronous Burst operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output enable. This Module has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as Quad Words in both Read and Write Operations.
August 1998 Rev. 1 ECO #10656
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White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
EDI2CG472256V
PIN CONFIGURATION PIN SYMBOLS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 FRONT VSS A0 A 16 A2 A14 VCC A4 A12 A6 A10 VSS A8 NC E4\ E2 \ VSS MODE EM\ GW\ NC1 VCC BW4\ BW3\ BW8\ BW7\ ADSC\ ADSP\ VSS NC2 VCC DQ0 DQ1 DQ2 DQ3 VSS ZZ1 VCC DQ8 DQ9 DQ10 DQ11 VSS PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 BACK VSS A17 A1 A15 A3 VCC A13 A5 A11 A7 VSS A9 NC3 E1\ E3 \ VSS CLK VSS G\ BWE\ VCC BW2\ BW1\ BW6\ BW5\ VSS ADV\ VSS DQP0 VCC DQ7 DQ6 DQ5 DQ4 VSS DQP1 VCC DQ15 DQ14 DQ13 DQ12 VSS PIN 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 FRONT NC4 VCC DQ16 DQ17 DQ18 DQ19 VSS ZZ2 VCC DQ24 DQ25 DQ26 DQ27 VSS NC5 VCC DQ32 DQ33 DQ34 DQ35 VSS ZZ3 VCC DQ40 DQ41 DQ42 DQ43 VSS NC6 VCC DQ48 DQ49 DQ50 DQ51 VSS ZZ4 VCC DQ56 DQ57 DQ58 DQ59 VSS PIN 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 BACK DQP2 VCC DQ23 DQ22 DQ21 DQ20 VSS DQP3 VCC DQ31 DQ30 DQ29 DQ28 VSS DQP4 VCC DQ39 DQ38 DQ37 DQ36 VSS DQP5 VCC DQ47 DQ46 DQ45 DQ44 VSS DQP6 VCC DQ55 DQ54 DQ53 DQ52 VSS DQP7 VCC DQ63 DQ62 DQ61 DQ60 VSS
PIN NAMES
DQ0-63 DQP0-7 A 0-17 EM\ Input/Output Bus Parity Bits Address Bus Address Enable
E1\, E2\, Synchronous Bank Enables E3\, E4\ BWE\ BW1-8\ CLK GW\ G\ Byte Write Mode Enable Byte Write Enables Array Clock Synchronous Global Write Enable Asynchronous Output Enable
ZZ1, ZZ2, Synchronous Bank Enables ZZ3, ZZ4 Vcc Vss NC 3.3V Power Supply Ground No Connect
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
2
EDI2CG472256V
FUNCTIONAL BLOCK DIAGRAM
ZZ1 E1\ MODE GW\ G\ EM\ CLK ADSC\ ADSP\ ADV\ A0-17 BW1\ BW2\ DQP0 DQP1 DQ0-15
ZZ2 E2\
ZZ3 E 3\
ZZ4 E4\
U1
U5
U9
U13
BW3\ BW4\ DQP2 DQP3 DQ16-31
U2
U6
U10
U14
BW5\ BW6\ DQP4 DQP5 DQ32-47
U3
U7
U11
U15
BW7\ BW8\ DQP6 DQP7 DQ48-63
U4
U8
U12
U16
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White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
EDI2CG472256V
PIN DESCRIPTIONS
DIMM Pins 2, 87, 4, 89, 7, 92 9, 94, 12, 96, 10 93, 8, 91, 5, 88, 3, 86 107, 106, 23, 22, 109, 108, 25, 24 104 19 101 98, 15, 99,14 103 111 27 26 Symbol A 0-17 Type Input Synchronous Description Addresses: These inputs are registered and must meet the setup and hold times around the rising edgeof CLK. The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle. Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW0/ controls DQ0-7 and DQP0, BW1\ controls DQ8-15 and DQP1. BW2\ controls DQ16-23 and DQP2. BW3\ controls DQ24-31 and DQP3. BW4\ controls DQ32-39 and DQP4. BW5\ controls DQ40-47 and BW6\ controls DQ48-55 and DQP6. BW7\ controls DQ56-64 and DQP7. Write Enable: This active LOW input gates byte write operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and BWx\ lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP\. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Status Processor: This active LOW input is used to control the internal burst counter. A HIGH on this pin generates wait cycle (no address advance). Address Status Processor: This active LOW input, along with EL\ and EH\ being LOW, causes a new external address to be registered and a READ cycle is initiated using the new address. Address Status Controller: This active LOW input causes device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs. Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST. Snooze: These active HIGH inputs put the individual banks in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (no connect). Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64. Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15. DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4\ is parity bit for DQ32-39. DQP5 is parity bit for DQ40-47. DQP6\ is parity bit for DQ48-55. DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device configured as a 128K x 64, the parity bits need to be tied to Vss through a 10K ohm resistor. Power supply: +3.3V -5%/+10% Ground
BW1\, BW2\, BW3\, BW4\, BW5\, BW6\, BW7\, BW8\ BWE\ GW\ CLK E1\, E2\ E3\, E4\ G\ ADV\ ADSP\ ADSC\
Input Synchronous
Input Synchronous Input Synchronous Input Synchronous Input Synchronous Input Input Synchronous Input Synchronous Input Synchronous Input Static Input Asynchronous Input/Output Input/Output
17 36, 50, 64, 78 Various 113, 120, 127, 134, 141, 148, 155, 162 Various Various
MODE ZZ1, ZZ2, ZZ3, ZZ4 DQ0-63 DQP0-7
Vcc Vss
Supply Ground
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
4
EDI2CG472256V
SYNCHRONOUS BURST - TRUTH TABLE
Operation Deselected Cycle, Power Down; Bank 1 Deselected Cycle, Power Down; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 2 Write Cycle, Begin Burst; Bank 1 Write Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 1 Read Cycle, Begin Burst; Bank 2 Read Cycle, Begin Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 1 Read Cycle, Continue Burst; Bank 2 Read Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 1 Write Cycle, Continue Burst; Bank 2 Write Cycle, Continue Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 1 Read Cycle, Suspend Burst; Bank 2 Read Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 1 Write Cycle, Suspend Burst; Bank 2 Write Cycle, Suspend Burst; Bank 2 E1\ H X L L H H L H L L H H X X H H H H H H X H H H X X H H H H H H X H H H E2\ X H H H L L H L H H L L H H X X H H H H H H X H H H X X H H H H H H X H E3\ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * E4\ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ADSP\ ADSC\ X L X L L X L X L X L X H L H L H L H L H L H L X H X H X H X H X H X H X H X H H H X H H H X H H H H H H H H H X H X H X H X H H H X H H H X H ADV\ X X X X X X X X X X X X L L L L L L L L L L L L H H H H H H H H H H H H GW\ X X X X X X L L H H H H H H H H H H H H L L L L H H H H H H H H L L L L G\ X X L H L H X X L H L H L H L H L H L H X X X X L H L H L H L H X X X X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z D D D D Q High-Z Q High-Z Q High-Z Q High-Z D D D D Addr. Used None None External External External External External External External External External External Next Next Next Next Next Next Next Next Next Next Next Next Current Current Current Current Current Current Current Current Current Current Current Current
*All Truth Table Functions Repeat for Bank 3 (E3\) and Bank 4 (E4\)
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White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
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