|
|
Part: EDI2GG464128V
Category:
Memory
-> SRAM
-> Modules->SSRAM->SSRAM Modules
Description: Organization = 4x128Kx64 ;; Speed (ns) = 10-12 ;; Volt = 3.3 ;; Package = 120 Ce-dimm ;; Temp = C ;;
Company: White Electronic Designs Corporation
Datasheet: Download EDI2GG464128V datasheet File size : 825 kB
Request For quote: Find where to buy EDI2GG464128V
Datasheet text preview:
EDI2GG464128V
4x128Kx64 Synchronous SRAM CARD EDGE DIMM, 3.3V
FEATURES
s 4x128Kx64 Synchronous s Access Speed(s): TKHQV = 9.5, 10, 11, 12, 15ns s Flow-Through Architecture s Clock Controlled Registered Bank Enables (E1\, E2\, E3, E4\) s Clock Controlled Registered Address s Clock Controlled Registered Global Write (GW\) s Aysnchronous Output Enable (G\) s Internally self-timed Write s Gold Lead Finish s 3.3V ±10%, -5% Operation s Common Data I/O s High Capacitance (30pF) drive, at rated Access Speed s Single total array Clock s Multiple Vcc and Vss The EDI2GG464128VxxD is a Synchronous SRAM, 60 position Card Edge DIMM (120 contacts) Module, organized as 4x128Kx64. The Module contains eight (8) Synchronous Burst Ram Devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The module architecture is defined as a Synchronous Only, Flow-Through, Early Write Device. This module provides High Performance, Ultra Fast access times at a cost per bit benefit over BiCMOS Asynchronous SRAM based devices. As well as improved cost per bit, the use of Synchronous or Synchronous Burst devices or modules can ease the memory subsystem design by reducing or easing the memory controller requirement. Synchronous operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output enable. All read and write operations to this module are performed on Quad Words (64 bit operations). Write cycles are internally self timed and are initiated by a rising clock edge. This feature relieves the designer the task of developing external write pulse width circuitry.
November 1998 Rev. 0 ECO# 10855
1
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
EDI2GG464128V
PIN CONFIGURATION
VSS A0 A1 A2 A3 VCC A4 A5 A6 A7 VSS A8 VSS CLK VSS E4\ VCC E3\ G\ VSS DQ0 DQ1 DQ2 DQ3 VCC D Q8 D Q9 DQ10 DQ11 VSS D Q16 D Q17 D Q18 D Q19 VCC D Q24 D Q25 D Q26 D Q27 VSS D Q32 D Q33 D Q34 D Q35 VCC D Q40 D Q41 D Q42 D Q43 VSS D Q48 D Q49 D Q50 D Q51 VCC D Q56 D Q57 D Q58 D Q59 VSS
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120
VSS A16 A15 A14 A13 VCC A12 A11 A10 A9 VSS RFU VSS NC VSS E2\ VCC E1\ GW\ VSS DQ7 DQ6 DQ5 DQ4 VCC D Q1 5 D Q14 D Q13 D Q12 VSS D Q23 D Q22 D Q21 D Q20 VCC D Q31 D Q30 D Q29 D Q28 VSS D Q39 D Q38 D Q34 D Q37 VCC D Q47 D Q46 D Q45 D Q44 VSS D Q55 D Q54 D Q53 D Q52 VCC D Q63 D Q62 D Q61 D Q60 VSS
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
2
EDI2GG464128V
FUNCTIONAL BLOCK DIAGRAM
A 0-16 GW\ G\
PIN NAMES
128Kx64
GW\ G\ E\ CLK DQ
128Kx64
GW\ G\ E\ CLK DQ
DQ0-63 A 0-15 E1-4\ CLK
Input/Output Bus Address Bus Synchronous Bank Enables Array Clock Synchronous Global Write Enable Asynchronous Output Enable 3.3V Power Supply Ground No Connect
E1\
GW\
128Kx64
GW\ G\ E\ CLK DQ
128Kx64
GW\ G\ E\ CLK DQ
G\ Vcc Vss
E2 \
NC
128Kx64
GW\ G\ E\ CLK DQ
128Kx64
GW\ G\ E\ CLK DQ
E3 \
128Kx64
GW\ G\ E\ CLK DQ
128Kx64
GW\ G\ E\ CLK DQ
E4 \ DQ0-63 CLK
PIN DESCRIPTIONS
DIMM Pins 3, 5, 7, 9, 13, 15, 17, 19, 20, 23, 18, 16, 14, 10, 8, 6 38 27 36, 32 35, 31 37 Various Various Various Symbol A0 - 1 5 Type Input Synchronous Input Synchronous Input Synchronous Input Synchronous Input Input/Output Supply Ground Description Addresses: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst and wait cycle. Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the BWE\ and BWx\ lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Bank Enables: These active LOW inputs are used to enable each individual bank and to gate ADSP\. Output Enable: This active LOW asynchronous input enables the data output drivers. Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64. Core power supply: +3.3V -5%/+10% Ground
GW\ CLK E1, E2\ E3\, E4\ G\ DQ 0-63 Vcc Vss
3
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
EDI2GG464128V
SYNCHRONOUS ONLY - TRUTH TABLE
Operation Synchronous Write-Bank 1 Synchronous Read-Bank 1 Synchronous Write-Bank 2 Synchronous Read-Bank 2 Synchronous Write-Bank 3 Synchronous Read-Bank 3 Synchronous Write-Bank 4 Synchronous Read-Bank 4 Snooze Mode E1\ L L H H H H H H X E2\ H H L L H H H H X E3\ H H H H L L H H X E4\ H H H H H H L L X GW\ L H L H L H L H X G\ H L H L H L H L X CLK X DQ High-Z High-Z High-Z High-Z High-Z
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Relative to Vss Vin Storage Temperature Operating Temperature (Commercial) Operating Temperature (Industrial) Short Circuit Output Current -0.5V to +4.6V -0.5V to Vcc +0.5V -55°C to +125°C 0°C to +70°C -40°C to +85°C 20 mA
RECOMMENDED DC OPERATING CONDITIONS
Parameter Supply Voltage Supply Voltage Input High Input Low Input Leakage Output Leakage Output High (IOH = -4mA) Output Low (IOL = 8mA) Sym VCC VSS VIH VIL ILI ILo VOH VOL Min 3.14 0.0 2.2 -0.3 -2 -2 2.4 Typ 3.3 0.0 3.0 0.0 1 1 Max 3.6 0.0 VCC +0.3 0.8 2 2 0.4 Units V V V V µA µA V V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Description Power Supply Current Power Supply Current
Device Selected,No Operation
Symbol Icc1 Icc IccZZ Icc3 IccK
Typ 1.55 0.75 200 400 600
9.5 2.8 1.8 300 500 900
10 2.2 1.5 300 500 900
Max 11 2.2 1.3 300 500 900
12 2.7 1.3 300 500 900
15 2.0 1.0 300 500 900
Units A A mA mA mA
Snooze Mode CMOS Standby Clock Running-Deselect
*TBD
AC TEST CIRCUIT
Parameter
AC TEST CONDITIONS
I/O VSS to 3.0 1.25 See figure, at left Unit V V
Output
ZZ0 = 50 0 = 50
50
Input Pulse Levels Input and Output Timing Levels Output Test Equivalencies
Vt = 1.5VV 1.25
A C Output Load Equivalent
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
4
EDI2GG464128V
READ CYCLE TIMING PARAMETERS
Description Clock Cycle Time Clock High Time Clock Low Time Clock to Output Valid Clock to Output Invalid Clock to Output Low-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Enable to Output High-Z Address Setup Bank Enable Setup Address Hold Bank Enable Hold
*TBD
Sym tKHKH tKHKL tKLKH tKHQV tKHQX1 tKHQX tGLQV tGLQX tGHQZ tAVKH tEVKH tKHAX tKHEX
Min * * * * * * * * * * * * *
9.5ns Max * * * * * * * * * * * * *
10ns Min 12 5 5 10 3 2 4 0 4 2.5 2.5 1.0 1.0 2.5 2.5 1.0 1.0 0 3 2 Max Min 12 5 5
11ns Max Min 15 5 5 11 3 2 5 0 5 2.5 2.5 1.0 1.0
12ns Max Min 20 6 6 12 3 2 5 0 5 2.5 2.5 1.0 1.0
15ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns
15
6 5
WRITE CYCLE TIMING PARAMETERS
Description Clock Cycle Time Clock High Time Clock Low Time Address Setup Address Hold Bank Enable Setup Bank Enable Hold Global Write Enable Setup Global Write Enable Hold Data Setup Data Hold
*TBD
Sym tKHKH tKHKL tKLKH tAVKH tKHAX tEVKH tKHEX tWVKH tKHWX tDVKH tKHDX
Min * * * * * * * * * * *
9.5ns Max * * * * * * * * * * *
10ns Min 12 5 5 2.5 1.0 2.5 1.0 2.5 1.0 2.5 1.0 Max Min 12 5 5 2.5 1.0 2.5 1.0 2.5 1.0 2.5 1.0
11ns Max Min 15 5 5 2.5 1.0 2.5 1.0 2.5 1.0 2.5 1.0
12ns Max Min 20 6 6 2.5 1.0 2.5 1.0 2.5 1.0 2.5 1.0
15ns Max Units ns ns ns ns ns ns ns ns ns ns ns
5
White Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
Others parts begin by ed
ED-1 ED-2 ED-3 ED-4 ED-5 ED-6
|
|
|
