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Part: EDI416S4030A
Category:
Memory
-> DRAM
-> SDR SDRAM
-> Industrial SDRAM
Description: Organization = 1Mx16x4 ;; Speed MHZ = 83-100 ;; Volt = 3.3 ;; Package = 54 Tsop ii ;; Temp = C,i ;;
Company: White Electronic Designs Corporation
Datasheet: Download EDI416S4030A datasheet File size : 825 kB
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Datasheet text preview:
White Electronic Designs
1M x 16 Bits x 4 Banks Synchronous DRAM
F E AT U R E S
n n n n n
Single 3.3V power supply Fully Synchronous to positive Clock Edge Clock Frequency = 100, 83MHz SDR AM CAS Latentency = 3 (100MHz), 2 (83MHz) Burst Operation ·Sequential or Interleave ·Burst length = programmable 1,2,4,8 or full page ·Burst Read and Write ·Multiple Burst Read and Single Write
EDI416S4030A
DESCRIPTION
The EDI416S4030A is 67,108,864 bits of synchronous high data rate DRAM organized as 4 x 1,048,576 words x 16 bits. Synchronous design allows precise cycle control with the use of system clock, I/O transactions are possible on ever y clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Available in a 54 pin TSOP type II package the EDI416S4030A is tested over the industrial temp range (-40C to +85C) providing a solution for rugged main memory applications.
n DATA Mask Control per byte n A uto Refresh (CBR) and Self Refresh
·4096 refresh cycles across 64ms
n A utomatic and Controlled Precharge Commands n Suspend Mode and Power Down Mode n Industrial Temperature Range
FIG. 1
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CE BA0 BA1 A10/AP A0 A1 A2 A3 VDD
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC/RFU UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
TERMINAL CONNECTIONS
PIN DESCRIPTION
A 0-11 BA0, BA1 CE WE CLK CKE DQ0-15 L(U)DQM RAS CAS VDD VDDQ VSS VSSQ NC Address Inputs Bank Select Addresses Chip Select Write Enable Clock Input Clock Enable Data Input/Output Data Input/Output Mask Row Address Strobe Column Address Strobe Power (3.3V) Data Output Power Ground Data Output Ground No Connection
(TOP VEIW)
Januar y 2003 Rev.2 E C O # 14194
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INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CLK CKE CE RAS, CAS WE BA0,BA1 Type Input Input Input Input Input Signal Pulse Level Pulse Pulse Level Polarity Positive Edge Active High Active Low Active Low --
EDI416S4030A
A0-11 , A 10 / A P
Input
Level
--
D Q0 - 1 5 L(U)DQM
Input/Output Input
Level Pulse
-- Mask Active High
VDD, VSS VDDQ, VSSQ
Supply Supply
Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CE disable or enable device operation by masking or enabling all inputs except CLK, CKE and DQM. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged . If A10/AP is low, autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge. Data Input/Output are multiplexed on the same pins. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. Power and ground for the input buffers and the core logic. Isolated power and ground for the output buffers to improve noise immunity.
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A BSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Shor t Circuit Output Current Symbol VDD VIN VOUT TOPR TSTG PD IO S Min -1.0 -1.0 -1.0 -40 -55 Max +4.6 +4.6 +4.6 +85 +125 1.0 50 Units V V V °C °C W mA
EDI416S4030A
RECOMMENDED DC OPERATING CONDITIONS (VOLTAGE REFERENCED TO: VSS = 0V, TA = -40°C TO +85°C)
Parameter S y m b o l Min Typ Max U n i t Notes Supply Voltage VDD 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 VDD +0.3 V Input Low Voltage VIL -0.3 -- 0.8 V Output High Voltage VOH 2.4 -- -- V (IOH = -2mA) Output Low Voltage VOL -- -- 0.4 V (IOL = 2mA) Input Leakage Voltage IIL -5 -- 5 mA Output Leakage Voltage IOL -5 -- 5 mA
Stresses greater than those listed under "Absolute Maximum Ratings" may cause per manent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25C, f = 1MHZ, VDD = 3.0V
Parameter Symbol Input Capacitance (A0-11, BA0-1) CI1 Input Capacitance (CLK, CKE, RAS, CI2 CAS, WE, CE, DQM) Input/Output Capacitance (DQ0-15) COUT
TO
3.6V)
Unit pF pF pF
Max 4 4 5
OPERATING CURRENT CHARACTERISTICS (V CC = 3.6V, TA = -40°C TO +85°C)
Parameter Operating Current (One Bank Active) Operating Current (Burst Mode) Precharge Standby Current in Power Down Mode Symbol I CC1 ICC4 I C C 2P I C C2 P S IC C 1 N ICC1NS Active Standby Current in Non-Power Down Mode I C C 3P I C C3 P S IC C 2 N ICC2NS ICC5 ICC6 Test Condition Burst Length = 1, tRC ³ tRC (min) Page Burst, 2 banks active, tCCD = 2 clocks CKE £ VIL (max), tCC = 15ns CKE, CLK £ VIL(max), tCC = ¥, Inputs Stable CKE = VIH, tCC = 15ns Input Change every 30ns CKE ³ VIH (min), tCC = ¥ No Input Change CKE £ VIL (max), tCC = 15ns CKE £ VIL (max), tCC = ¥ CKE = VIH, tCC = 15ns Input Change every 30ns CKE ³ VIH (min), tCC = ¥, No Input Change tRC ³ tRC (min) CKE £ 0.2V -10 140 200 2 2 50 35 12 12 30 20 210 3 -12 125 165 2 2 50 35 12 12 30 20 210 3 U n i t s Notes mA 1 mA 1 mA mA mA mA mA mA mA mA mA mA
Precharge Standby Current in Non-Power Down Mode
Active Standby Current in Power Down Mode Refresh Current Self Refresh Current
2
NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms.
3
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AC CHARACTERISTICS
OPERATING AC PARAMETIERS (VCC = 3.0V TO 3.6V, TA = -40°C TO +85°C)
Parameter Clock Cycle Time Clock to Valid Output Delay Output Data Hold Time Clock High Pulse Width Clock Low Pulse Width Input Setup Time Input Hold Time Clock to Output in Low-Z Clock to Output in High-Z Row Active to Row Active Delay RAS to CAS Delay Row Precharge Time Row Active Time Row Cycle Time - Operation Row Cycle Time - Auto Refresh Last Data In to New Column Address Delay Last Data In to Row Precharge Last Data In to Burst Stop Column Address to Column Address Delay Number of Valid Output Data CAS latency = 3 CAS latency = 2 Symbol tC C tS A C tOH tCH tCL tSS tSH tS L Z tSHZ tRRD tRCD tRP t RAS tRC tR F C tCDL tR D L tB D L t CCD CAS latency = 3 CAS latency = 2 Min 10 13 3 3.5 3.5 2.5 1 1 7 20 24 24 50 80 80 1 1 1 1 2 1 -10 Max 1000 1000 7
EDI416S4030A
Min 12 15 3 4.0 4.0 3 1 1
-12
Max 1000 1000 8
U n i t s Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK ea 1 1, 2 2 3 3 3 3 2 4 4 4 4 4 4, 8 5 5 5 6 7
8 24 26 26 60 90 90 1 1 1 1 2 1
100,000
100,000
NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns, (trise/2 - 0.5ns) should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If trise & tfall are longer than 1ns, [(trise + tfall)/2]-1ns should be added to the parameter. 4. The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. All devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self refresh exit.
REFRESH CYCLE PARAMETERS
Parameter Refresh Period Self Refresh Exit Time Symbol t REF tSREX Min -- tR F C -10 Max 64 -- Min -- tRFC -12 Max 64 -- Units ms ns Notes 1, 2 3
NOTES: 1. 4096 cycles. 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 3. The self refresh is exited by restarting the external clock and then asserting CKE high. This must be followed by NOPs for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation.
W h i t e Electronic Designs Corporation · Westborough, MA · (508) 366-5151
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CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHZ (U NITS = NUMBER OF CLOCKS)
Frequency 100MHz (10ns) 83MHz (12ns) 75MHz (12ns) 66MHz (15ns) CAS Latency 3 3 2 2 tRC 80ns 8 7 6 6 tRAS 50ns 5 5 4 4 t RP 24ns 3 2 2 2 t RRD 20ns 2 2 2 2 t RCD 24ns 3 2 2 2
EDI416S4030A
t CCD 10ns 1 1 1 1
t CDL 10ns 1 1 1 1
t RDL 10ns 1 1 1 1
CLOCK FREQUENCY AND LATENCY PARAMETERS - 83MHZ (U NITS = NUMBER OF CLOCKS)
Frequency 83MHz (12ns) 75MHz (13ns) 66MHz (15ns) CAS Latency 3 3 2 tRC 90ns 8 7 6 tRAS 60ns 5 5 4 t RP 26ns 3 2 2 t RRD 24ns 2 2 2 t RCD 26ns 3 2 2 t CCD 12ns 1 1 1 t CDL 12ns 1 1 1 t RDL 12ns 1 1 1
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W h i t e Electronic Designs Corporation · (508) 366-5151 · www.whiteedc.com
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