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Part: EDI88128CS-55C
Category:
Memory
-> SRAM
-> SRAM
Description: Organization = 128Kx8 ;; Speed (ns) = 15-55 ;; Volt = 5 ;; Package = 32 Zip ;; Temp = C,i,m,b ;;
Company: White Electronic Designs Corporation
Datasheet: Download EDI88128CS-55C datasheet File size : 576 kB
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Datasheet text preview:
EDI88128CS
HI-RELIABILITY PRODUCT
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
s Access Times of 15*, 17, 20, 25, 35, 45, 55ns s CS and OE Functions for Bus Control s 2V Data Retention (EDI88128LPS) s TTL Compatible Inputs and Outputs s Fully Static, No Clocks s Organized as 128Kx8 s Commercial, Industrial and Military Temperature Ranges s Thru-hole and Surface Mount Packages JEDEC Pinout · 32 pin Ceramic DIP, 400 mil (Package 102) · 32 pin Ceramic DIP, 600 mil (Package 9) · 32 lead Ceramic ZIP (Package 100) · 32 lead Ceramic SOJ (Package 140) · 32 pad Ceramic LCC (Package 141) · 32 lead Ceramic Flatpack (Package 142) s Single +5V (±10%) Supply Operation The EDI88128CS is a high speed, high performance, 128Kx8 megabit density Monolithic CMOS Static RAM. The device has eight bi-directional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. A Low Power version with 2V Data Retention (EDI88128LPS) is also available for battery back-up opperation. Military product is available compliant to MIL-PRF-38535.
* 15ns access time is advanced information, contact factory for availability.
FIG. 1
PIN CONFIGURATION
32 32 32 32 DIP SOJ LCC FLATPACK
PIN DESCRIPTION
I/O0-7 A0-16 Data Inputs/Outputs Address Inputs Write Enable Chip Select Output Enable Power (+5V ±10%) Ground Not Connected
32 ZIP
TOP VIEW
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 V CC 31 A15 30 NC 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CS 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS
TOP VIEW
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 VC C 4 A15 6 NC 8 WE 10 A13 12 A8 14 A9 16 A11 18 OE 20 A10 22 CS 24 I/O7 26 I/O6 28 I/O5 30 I/O4 32 I/O3
AØ-16
WE CS OE VCC VSS NC
BLOCK DIAGRAM
Memory Array
Address Buffer
Address Decoder
I/O Circuits
I/OØ-7
WE CS OE
February 2000 Rev. 10
1
White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com
EDI88128CS
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature, TJ 0 to +70 -40 to +85 -55 to +125 -65 to +150 1.5 20 175 °C °C °C °C W mA °C -0.5 to 7.0 Unit V OE X H L X CS H L L L WE X H H L
TRUTH TABLE
Mode Standby O u t p u t Deselect Read Write Output High Z High Z D a t a Out D a t a In Power I c c 2 , Icc3 Icc1 Icc1 Icc1
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VC C VS S VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 -- -- Max 5.5 0 Vcc +0.5 +0.8 Unit V V V V
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C)
Max Parameter Symbol Condition
CSOJ,
Unit
LCC ZIP, DIP,
Flatpack
Address Lines Data Lines
CI CO
VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz
6 8
12 14
pF pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS (VCC = 5V, TA = -55°C to +125°C)
Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Symbol ILI ILO I CC1 VIN = 0V to VCC VI/O = 0V to VCC (15-17ns) W E , CS = VIL, II/O = 0mA, Min Cycle (20ns) (25-55ns) Standby (TTL) Power Supply Current I CC2 C S VIH, VIN VIL, VIN VIH C S VCC -0.2V VIN Vcc -0.2V or VIN 0.2V IOL = 8.0mA IOH = -4.0mA (17-55ns) (15ns) CS (17-55ns) CS (15ns) LPS Output Low Voltage Output High Voltage VO L VO H Full Standby Power Supply Current I CC3 Conditions Min -- -- -- -- -- -- -- -- -- -- -- 2.4 3 -- -- -- -- Typ -- -- Max ±5 ±10 300 225 200 25 60 10 15 5 0.4 -- µA µA mA mA mA mA mA mA mA mA V V Units
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
White Electronic Designs Corporation · (602) 437-1520 · ww.whiteedc.com
2
EDI88128CS
AC CHARACTERISTICS READ CYCLE (15 to 20ns) (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Chip Enable to Power Up (1) Chip Enable to Power Down (1) Symbol JEDEC Alt. tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ tELICCH tEHICCL tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ tPU tPD 0 15 0 6 0 17 0 6 0 6 0 20 3 8 0 6 0 8 15ns* Min 15 15 15 3 8 0 8 Max Min 17 17 17 3 10 17ns Max Min 20 20 20 20ns Max Units ns ns ns ns ns ns ns ns ns ns ns
1 . This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS READ CYCLE (25 to 55ns) (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Chip Enable to Power Up (1) Chip Enable to Power Down (1) Symbol JEDEC Alt. tAVAV tAVQV tELQV tELQX tEHQZ tAVQX tGLQV tGLQX tGHQZ tELICCH tEHICCL tRC tAA tACS tCLZ tCHZ tOH tOE tOLZ tOHZ tPU tPD 0 25 0 10 0 35 0 10 0 15 0 45 3 12 0 15 0 20 0 55 25ns Min 25 25 25 3 20 0 20 0 20 Max Min 35 35 35 3 20 0 25 35ns Max Min 45 45 45 3 20 45ns Max Min 55 55 55 55ns Max Units ns ns ns ns ns ns ns ns ns ns ns
1 . This parameter is guaranteed by design but not tested.
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480 Q 255 30pF Q 255
480
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load
VSS to 3.0V 5ns 1.5V Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
5pF
3
White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com
EDI88128CS
AC CHARACTERISTICS WRITE CYCLE (12 to 20ns) (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Symbol JEDEC Alt. tAVAV tELWH tELEH tAVWL tAVEL tAVWH tAVEH tWLWH tWLEH tWHAX tEHAX tWHDX tEHDX tWLQZ tDVWH tDVEH tWHQX tWC tCW tCW tAS tAS tAW tAW tWP tWP tWR tWR tDH tDH tWHZ tDW tDW tWLZ 15ns* Min 15 12 12 0 0 12 12 12 12 0 0 0 0 0 7 7 3 8 Max Min 17 13 13 0 0 13 13 13 13 0 0 0 0 0 7 7 3 8 17ns Max Min 20 15 15 0 0 15 15 15 15 0 0 0 0 0 10 10 3 10 20ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS WRITE CYCLE (25 to 55ns) (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Symbol JEDEC Alt. tAVAV tELWH tELEH tAVWL tAVEL tAVWH tAVEH tWLWH tWLEH tWHAX tEHAX tWHDX tEHDX tWLQZ tDVWH tDVEH tWHQX tWC tCW tCW tAS tAS tAW tAW tWP tWP tWR tWR tDH tDH tWHZ tDW tDW tWLZ 25ns Min 25 20 20 0 0 20 20 20 20 0 0 0 0 0 15 15 3 10 Max Min 35 25 25 0 0 25 25 30 30 0 0 0 0 0 20 20 3 13 35ns Max Min 45 35 35 0 0 35 35 30 30 5 5 0 0 0 20 20 3 15 45ns Max Min 55 45 45 0 0 45 45 35 35 5 5 0 0 0 25 25 3 20 55ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corporation · (602) 437-1520 · ww.whiteedc.com
4
EDI88128CS
FIG. 2
TIMING WAVEFORM - READ CYCLE
ADDRESS
tAVAV tAVQV
CS
tAVAV
ADDRESS
ADDRESS 1 ADDRESS 2
tELQV tELQX tELICCH
Icc
tEHQZ tEHICCL
tAVQV
DATA I/O
tAVQX
DATA 1 DATA 2
OE
tGLQV tGLQX
DATA I/O
tGHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (WE HIGH)
FIG. 3
WRITE CYCLE - WE CONTROLLED
tAVAV
ADDRESS
tAVWH tELWH
CS
tWHAX
tAVWL
WE
tWLWH tDVWH tWHDX
DATA IN
DATA VALID
tWLQZ
DATA OUT
HIGH Z
tWHQX
WRITE CYCLE 1, WE CONTROLLED
FIG. 4
WRITE CYCLE - CS CONTROLLED
ADDRESS
tAVAV
WS32K32-XHX
tAVEH tELEH tEHAX tAVEL tWLEH tDVEH tEHDX
CS
WE
DATA IN DATA OUT
HIGH Z
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
5
White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com
Others parts begin by ed
ED-1 ED-2 ED-3 ED-4 ED-5 ED-6
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