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Part: EDI88128LP-100B
Category:
Memory
-> SRAM
-> SRAM
Description: Organization = 128Kx8 ;; Speed (ns) = 70-120 ;; Volt = 5 ;; Package = 32 Dip ;; Temp = C,i,m,b ;;
Company: White Electronic Designs Corporation
Datasheet: Download EDI88128LP-100B datasheet File size : 576 kB
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Datasheet text preview:
EDI88128C
HI-RELIABILITY PRODUCT
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
s Access Times of 70, 85, 100ns s Available with Single Chip Selects (EDI88128) or Dual Chip Selects (EDI88130) s 2V Data Retention (LP Versions) s CS and OE Functions for Bus Control s TTL Compatible Inputs and Outputs s Fully Static, No Clocks s Organized as 128Kx8 s Industrial, Military and Commercial Temperature Ranges s Thru-hole and Surface Mount Packages JEDEC Pinout · 32 pin Ceramic DIP, 0.6 mils wide (Package 9) · 32 lead Ceramic ZIP (Package 100) · 32 lead Ceramic SOJ (Package 140) s Single +5V (±10%) Supply Operation The EDI88128C is a high speed, high performance, Monolithic CMOS Static RAM organized as 128Kx8. The device is also available as EDI88130C with an additional chip select line (CS2) which will automatically power down the device when proper logic levels are applied. The second chip select line (CS2) can be used to provide system memory security during power down in non-battery backed up systems and simplifiy decoding schemes in memory banking where large multiple pages of memory are required. The EDI88128C and the EDI88130C have eight bi-directional input-output lines to provide simultaneous access to all bits in a word. An automatic power down feature permits the on-chip circuitry to enter a very low standby mode and be brought back into operation at a speed equal to the address access time. Low power versions, EDI88128LP and EDI88130LP, offer a 2V data retention function for battery back-up opperation. Military product is available compliant to Appendix A of MIL-PRF-38535.
FIG. 1
PIN CONFIGURATION PIN DESCRIPTION
32 DIP 32 SOJ 32 ZIP
I/O0-7 A0-16 WE Data Inputs/Outputs Address Inputs Write Enable Chip Selects Output Enable Power (+5V ±10%) Ground Not Connected
TOP VIEW
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 NC/CS2* WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 AØ I/OØ I/O1 I/O2 VSS
TOP VIEW
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 VCC A15 NC/CS2* WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3
CS1, CS2 OE VCC VSS NC
BLOCK DIAGRAM
Memory Array
AØ-16
Address Buffer
Address Decoder
I/O Circuits
I/OØ-7
WE CS1 CS2 OE
* Pin 30 is NC for 88128 or CS2 for 88130.
July 1999 Rev. 13
1
White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com
EDI88128C
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Operating Temperature TA (Ambient) Commercial Industrial Military Storage Temperature, Plastic Power Dissipation Output Current Junction Temperature, TJ 0 to +70 -40 to +85 -55 to +125 -65 to +150 1 20 175 °C °C °C °C W mA °C -0.5 to 7.0 Unit V OE X X X H L X C S1 H X X L L L CS2 X L L H H H WE X X X H H L
TRUTH TABLE
Mode Standby Standby O u t p u t Deselect O u t p u t Deselect Read Write Output High Z High Z High Z High Z D a t a Out D a t a In Power I c c 2 , Icc3 I c c 2 , Icc3 Icc1 Icc1 Icc1 Icc1
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Symbol VC C VS S VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 -- -- Max 5.5 0 Vcc +0.5 +0.8 Unit V V V V
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (T A = +25°C)
Parameter Address Lines Input/Output Lines Symbol CI CO Condition VIN = Vcc or Vss, f = 1.0MHz VOUT = Vcc or Vss, f = 1.0MHz Max 12 14 Unit pF pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS (VCC = 5V, TA = +25°C)
Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current Output Low Voltage Output High Voltage Symbol ILI ILO I CC1 I CC2 I CC3 VO L VO H VIN = 0V to VCC VI/O = 0V to VCC, CS1 VIH and/or CS2 VIL W E , CS1 = VIL, II/O = 0mA, Min Cycle CS2 = VIH (70-85ns) (100ns) C LP Conditions Min -5 -10 -- -- -- -- -- -- 2.4 1 -- -- -- Typ -- -- Max +5 +10 120 110 10 5 1 0.4 -- µA µA mA mA mA mA mA V V Units
C S 1 VIH and/or CS2 VIL, VIN VIH or VIL C S 1 VCC -0.2V and/or CS2 Vcc +0.2V VIN Vcc -0.2V or VIN 0.2V IOL = 2.1mA IOH = -1.0mA
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com
2
EDI88128C
AC CHARACTERISTICS READ CYCLE (VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C)
Parameter Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z (1) Symbol JEDEC Alt. tAVAV tAVQV tELQV tSHQV tELQX tSHQX tEHQZ tSLQZ tAVQX tGLQV tGLQX tGHQZ tRC tAA tACS tACS tCLZ tCLZ tCHZ tCHZ tOH tOE tOLZ tOHZ 0 0 30 3 3 0 0 3 25 0 0 30 30 30 70ns Min 70 70 70 70 3 3 0 0 3 30 0 0 30 30 30 Max Min 85 85 85 85 3 3 0 0 3 50 30 30 85ns Max Min 100 100 100 100 100ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns
1 . This parameter is guaranteed by design but not tested.
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480 Q 255 30pF Q 255
480
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load
VSS to 3.0V 5ns 1.5V Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
5pF
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White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com
EDI88128C
AC CHARACTERISTICS WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C)
Parameter Write Cycle Time Chip Select to End of Write Symbol JEDEC Alt. tAVAV tELWH tELEH tSHWH tSHSL tAVWL tAVEL tAVSH tAVWH tWLWH tWLEH tWLSL tWHAX tEHAX tSLAX tWHDX tEHDX tSLDX tWLQZ tDVWH tDVEH tDVSL tWHQX tWC tCW tCW tCW tCW tAS tAS tAS tAW tWP tWP tWP tWR tWR tWR tDH tDH tDH tWHZ tDW tDW tDW tWLZ 70ns Min 70 60 60 60 60 0 0 0 60 35 35 35 5 5 5 0 0 0 0 35 35 35 5 30 Max Min 85 75 75 75 75 0 0 0 75 70 70 70 5 5 5 0 0 0 0 40 40 40 5 35 85ns Max Min 100 85 85 85 85 0 0 0 85 80 80 80 5 5 5 0 0 0 0 40 40 40 5 40 100ns Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Address Setup Time
Address Valid to End of Write Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1) Data to Write Time
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com
4
EDI88128C
FIG. 2
TIMING WAVEFORM - READ CYCLE
tAVAV
ADDRESS
tAVQV
CS1
tAVAV
ADDRESS
tELQV tELQX
CS2
ADDRESS 2
tEHQZ
ADDRESS 1
tSHQV tSHQX
OE
DATA 2
tSLQZ
tAVQV
DATA I/O
tAVQX
DATA 1
tGLQV t GLQX
DATA I/O
t GHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (WE HIGH)
FIG. 3
WRITE CYCLE 1
ADDRESS
tA V A V tA V W H tW L W H
tA V W L
WE
tW H A X
CS1
tELWH
CS2
tS H W H
DATA IN
tD V W H
tW H Q X tW H D X
DATA VALID
tW L Q Z
DATA OUT
HIGH Z
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
FIG. 4
WRITE CYCLE2
tAVAV
ADDRESS
WRITE CYCLE 3
WS32K32-XHX
ADDRESS
tAVAV tSLAX
tAVEL
WE
tWLEH
tEHAX
WE
tAVSH
tWLSL
tELEH
CS1
tSHSL
CS1
CS2
CS2
tDVEH
DATA IN
DATA VALID
tEHDX
DATA IN
tDVSL
DATA VALID
tSLDX
WRITE CYCLE 2 - EARLY WRITE, CS1 CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
5
White Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com
Others parts begin by ed
ED-1 ED-2 ED-3 ED-4 ED-5 ED-6
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