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Part: EDI9LC644V-BC
Category:
Memory
-> Multi Chip Memory
-> SSRAM/SRAM MCP
Description: Organization = 128Kx32/1Mx32 ;; Speed MHZ = 133-200/100-125 ;; Volt = 3.3 ;; Package = 153 Bga ;; Temp = C,i,m ;;
Company: White Electronic Designs Corporation
Datasheet: Download EDI9LC644V-BC datasheet File size : 612 kB
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Datasheet text preview:
EDI9LC644V
128Kx32 SSRAM/1Mx32 SDRAM
EXTERNAL MEMORY SOLUTION FOR TEXAS INSTRUMENTS TMS320C6000 DSP
F E AT U R E S DESCRIPTION
n Clock speeds:
· SSRAM: 200, 166,150, and 133 MHz · SDRAMs: 125 and 100 MHz
n n n n n n n
DSP Memory Solution · Texas Instruments TMS320C6201 · Texas Instruments TMS320C6701 Packaging: · 153 pin BGA, JEDEC MO-163 3.3V Operating supply voltage Direct control interface to both the SSRAM and SDRAM por ts on the "C6x" Common address and databus 65% space savings vs. monolithic solution Reduced system inductance and capacitance
The EDI9LC644VxxBC is a 3.3V, 128K x 32 Synchronous Pipeline SRAM and a 1Mx32 Synchronous DRAM array cons t r u c t e d with one 128K x 32 SBSRAM and two 1Mx16 SDR AM die mounted on a multilayer laminate substrate. The device is packaged in a 153 lead, 14mm by 22mm, BGA. The EDI9LC644VxxBC provides a total memory solution for t h e Texas Instr u m e n t s TMS320C6201 and the TMS320C6701 DSPs T h e Synchronous Pipeline SRAM is available with clock speeds of 200, 166,150, and 133 MHz, allowing the user to develop a fast external memory for the SSRAM interface port . The SDRAM is available in clock speeds of 125 and 100 MHz, allowing the user to develop a fast external memory for the SDRAM interface port .
FIG. 1
PIN CONFIGURATION
B O T T O M VIEW P I N DESCRIPTION
7 8 9 2 3 4 5 6
1 A B C D E F G H J K L M N P R T U
A0-16
A B C D E F G H J K L M N P R T U
Address Bus Data Bus SSRAM Clock SSRAM Address Status Control SSRAM Write Enable SSRAM Output Enable SDRAM Clock SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Write Enable SDRAM Address 10/auto precharge SSRAM Byte Write Enables SDRAM SDQM 0 - 3 Chip Enable SSRAM Device Chip Enable SDRAM Device Power Supply pins, 3.3V Data Bus Power Supply pins, 3.3V (2.5V future) Ground No Connect
D Q 19 D Q 18 V CCQ D Q 17 D Q 16 V CCQ NC NC A6 NC V CCQ D Q 12 D Q 13 V CCQ D Q 14 D Q 15
1
D Q 23 D Q 22 V CCQ D Q 21 D Q 20 V CCQ NC NC A7 NC V CCQ D Q 11 D Q 10 V CCQ DQ 9 DQ 8
2
VC C VC C VC C VC C VC C VC C NC A8 A9 NC VC C VC C VC C VC C VC C
3
VS S VS S VS S VS S VS S VS S VS S VS S
VSS SDCE VSS SDCLK VSS VSS VS S VSS
VSS VSS NC VSS VSS VSS NC NC NC NC NC VSS VSS VSS NC NC
6
VC C VC C VC C VC C VC C VC C A2 A1 A0 NC NC VC C VC C VC C VC C VC C VC C
7
D Q 24 D Q 25 V CCQ D Q 26 D Q 27 V CCQ A4 A3 A11 A 13 A 15 V CCQ DQ 4 DQ 5 V CCQ DQ 6 DQ 7
8
D Q 28 D Q 29 V CCQ D Q 30 D Q 31 V CCQ A5 A 10 A12 A 14 A 16 V CCQ DQ 0 DQ 1 V CCQ DQ 2 DQ 3
9
DQ0-31 SSCLK SSADC SSWE SSOE SDCLK SDRAS SDC A S SDWE SDA10 BWE0-3 SSCE SDCE VCC VCCQ VSS NC
SDWE SDA10
SDR A S S D C A S V S S
NC/A17 NC/A18 NC/A19
BWE 2 BWE 3 BWE 0 BWE 1 VS S VS S VS S VSS S SCLK VSS
VC C S SADC S SWE S SOE S SCE
4 5
J a n u a r y 2002 Rev. 4 E C O # 14667
1
W h i t e Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com
EDI9LC644V
FIG. 2
BLOCK DIAGRAM
W h i t e Electronic Designs Corporation · Phoenix AZ · (602) 437-1520
2
EDI9LC644V
O U T P U T FUNCTIONAL DESCRIPTIONS
Symbol Ty p e Signal Polarity Function
S SCLK S SADS S SOE S SWE S SCE SDCLK SDCE SDR A S SDC A S SDWE
Input Input Input Input Input Input
Pulse Pulse Pulse Pulse Pulse Pulse
Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock. Active Low Active Low When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation to be executed by the SSRAM. S SCE disable or enable SSRAM device operation.
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Active Low Active Low SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3. When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the operation to be executed by the SDRAM. Address bus for SSRAM and SDRAM A0 and A1 are the burst address inputs for the SSRAM During a Bank Active command cycle, A0-9, SDA10 defines the row address (RA0-10) when sampled at the rising clock edge.
A 0-16 , SDA10
Input
Level
--
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A11 defines the bank to be precharged (low = bank A, high = bank B). If SDA10 is low, autoprecharge is disabled. During a Precharge command cycle, SDA10 is used in conjunction with A11 to control which bank(s) to precharge. If SDA10 is high, both bank A and Bank B will be precharged regardless of the state of A11. If SDA10 is low, then A11 is used to define which bank to precharge.
D Q 0-31 BWE 0 - 3 VCC, VSS VC C Q
Input Output Input Supply Supply
Level Pulse
--
Data Input/Output are multiplexed on the same pins. BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31. Power and ground for the input buffers and the core logic. Data base power supply pins, 3.3V (2.5V future).
3
W h i t e Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com
EDI9LC644V
A B S O L U T E MAXIMUM RATINGS
Voltage on Vcc Relative to Vss Vin (DQx) Storage Temperature (BGA) J u n c t i o n Temperature Short Circuit Output Current -0.5V to +4.6V -0.5V to Vcc +0.5V -55°C to +125°C +175°C 1 0 0 mA
R E C O M M E N D E D DC OPERATING CONDITIONS
( 0 ° C TA 70°C; V C C = 3.3V -5% / +10%
Parameter UNLESS OTHERWISE NOTED) Min Max Units
Symbol
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Supply Voltage1 Input High Voltage1,2 Input Low Voltage1,2 Input Leakage Current 0 - VIN - V c c Output Leakage (Output Disabled) 0 - VIN - V c c Output High (IOH = -4mA)1 Output Low (IOL = 8mA)1
NOTES:
V CC VIH VIL IL I IL O VOH V OL
3.135 2.0 -0.3 -10 -10 2.4 --
3.6 VCC +0.3 0.8 10 10 -- 0.4
V V V µA µA V V
1. All voltages referenced to Vss (GND). 2. Overshoot: VIH +6.0V for t - tKC/2 Underershoot: VIL -2.0V for t - tKC/2
£
³
D C ELECTRIC A L CHARACTERISTICS
Description Conditions Symbol Frequency Ty p Max Units
Power Supply Current: Operating (1,2,3)
S SRAM Active / DRAM Auto Refresh
I CC 1
Power Supply Current Operating 1,2,3
S SRAM Active / DRAM Idle
I CC 2
Power Supply Current Operating 1,2,3
SDR AM Active / SSRAM Idle S SCE and SDCE VCC -0.2V, All other inputs at VSS +0.2 VIN or VIN VCC -0.2V, Clk frequency = 0 S SCE and SDCE VIH min All other inputs at VIL max VIN or VIN VCC -0.2V, Clk frequency = 0
I CC 3
CMOS Standby
£
133MHz 150MHz 166MHz 200MHz 133MHz 150MHz 166MHz 200MHz 83MHz 100MHz 125MHz
£ £
£
I SB 1
400 450 500 TBD 300 350 400 TBD 220 235 255 20.0
550 580 625 TBD 450 480 525 TBD 240 250 280 40.0
mA
mA
mA
mA I SB 2 30.0 55.0 mA I CC 5 190 250 mA
TTL Standby Auto Refresh
NOTES:
£
£
1. ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading. 2. "Device idle" means device is deselected (CE VIH) Clock is running at max frequency and Addresses are switching each cycle. 3. Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency.
³
B G A C A PAC I TA N C E
Description Conditions Symbol Typ Max Units
A d d r e s s Input Capacitance 1 I n p u t / O u t p u t Capacitance (DQ)1 C o n t r o l Input Capacitance1 C l o c k Input Capacitance 1
NOTE:
TA = 25°C; f = 1MHz TA = 25°C; f = 1MHz TA = 25°C; f = 1MHz TA = 25°C; f = 1MHz
CI CO CA CCK
5 8 5 4
8 10 8 6
pF pF pF pF
1. This parameter is sampled.
W h i t e Electronic Designs Corporation · Phoenix AZ · (602) 437-1520
4
EDI9LC644V
S S R A M AC CHARACTERISTICS (EDI9LC644V)
Symbol Parameter 200MHz Min Max 166MHz Min Max 150MHz Min Max 133MHz Min Max Units
C l o c k Cycle Time C l o c k HIGH Time C l o c k LOW Time C l o ck to output valid C l o c k to output invalid C l o c k to output on Low-Z C l o c k to output in High-Z O u t p u t Enable to output valid O u t p u t Enable to output in Low-Z O u t p u t Enable to output in High-Z A d d r e s s , Control, Data-in Setup Time to Clock A d d r e s s , Control, Data-in Hold Time to Clock
t KHKH tK L K H tK H K L tK H Q V tK H Q X tKQLZ tK Q H Z tO E L Q V tO E L Z tOEHZ tS tH
5 1.6 1.6 2.5 1.5 0 1.5 0 3.0 1.5 0.5
6 2.4 2.4 3.5 1.5 0 1.5 0 3.5 1.5 0.5
7 2.6 2.6 3.8 1.5 0 1.5 0 3.5 1.5 0.5
8 2.8 2.8 4.0 1.5 0 1.5 0 3.8 1.5 0.5
3 2.5
3.5 3.5
3.8 3.8
4.0 4.0
ns ns ns ns ns ns ns ns ns ns ns ns
S S R A M OPERATION TRUTH TABLE
Operation Address Used S SCE S SADS S SWE S SOE DQ
Deselected Cycle, Power Down WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst
Note:
None Exter nal Exter nal Exter nal Cur rent Cur rent Cur rent Cur rent Cur rent Cur rent
H L L L X X H H X H
L L L L H H H H H H
X L H H H H H H L L
X X L H L H L H X X
High-Z D Q High-Z Q High-Z Q High-Z D D
1. X means "don't care", H means logic HIGH. L means logic LOW. 2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK. 3. Suspending burst generates wait cycle 4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH though out the input data hold time. 5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
S S R A M PARTIAL TRUTH TABLE
Function S SWE BWE0 BWE1 BWE2 BWE3
READ WRITE one Byte (DQ0-7) WRITE all Bytes
H L L
X L L
X H L
X H L
X H L
5
W h i t e Electronic Designs Corporation · (602) 437-1520 · www.whiteedc.com
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