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Details, datasheet, quote on part number:WED3DL328V-12
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| Part: | WED3DL328V-12 |
| Category: | Memory => DRAM => SDR SDRAM => SDRAM MCP |
| Description: | Organization = 8Mx32 ;; Speed MHZ = 100-133 ;; Volt = 3.3 ;; Package = 119 Pbga ;; Temp = C,i,m ;; |
| Company: | White Electronic Designs Corporation |
| Datasheet: | Download WED3DL328V-12 datasheet File size : 438 kB |
| Request For quote: | Find where to buy WED3DL328V-12
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Datasheet text preview:
White Electronic Designs
8Mx32 SDRAM
FEATURES
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53% Space Savings vs. Monolithic Solution Reduced System Inductance and Capacitance Pinout and Footprint Compatible to SSRAM 119 BGA 3.3V Operating Supply Voltage Fully Synchronous to Positive Clock Edge Clock Frequencies of 133MHz, 125MHz and 100MHz Burst Operation Sequential or Interleave Burst Length = Programmable 1, 2, 4, 8 or Full Page Burst Read and Write Multiple Burst Read and Single Write
WED3DL328V
DESCRIPTION
The WED3DL328V is an 8Mx32 Synchronous DRAM configured as 4x2Mx32. The SDRAM BGA is constructed with two 8Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 119 lead, 14mm by 22mm, BGA. The WED3DL328V is an ideal SDRAM wide I/O memory solution for all high performance, computer applications which include Network Processors, DSPs and Functional ASICs. The WED3DL328V is available in clock speeds of 133MHz, 125MHz and 100MHz. The range of operati n g frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The package and design provides performance enhancements via a 50% reduction in capacitance vs. two monolithic devices. The design includes internal ground and power planes which reduces inductance on the ground and power pins allowing for improved decoupling and a reduction in system noise.
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Data Mask Control Per Byte Auto and Self Refresh Automatic and Controlled Precharge Commands Suspend Mode and Power Down Mode 119 Pin BGA, JEDEC MO-163
FIG. 1
1 A B C D E F G H J K L M N P R T U V DDQ NC NC DQC DQC V DDQ DQC DQC V DDQ DQD DQD V DDQ DQD DQD NC NC V DDQ 1 2 NC NC NC NC DQC DQC DQC DQC VDD DQD DQD DQD DQD NC A6 NC NC 2
PIN CONFIGURATION (TOP VIEW)
3 BA 0 N C / A 12 * BA 1 VS S VS S VS S DQMC VS S NC VS S DQMD VS S VS S VS S NC A5 NC 3 4 NC CAS VDD NC CE RAS NC CKE VDD CLK NC WE A1 A0 VDD A4 NC 4 5 A 10 A 11 A9 VS S VS S VS S DQMB VS S NC VS S DQMA VS S VS S VS S NC A3 NC 5 6 A7 NC A8 NC DQB DQB DQB DQB VDD DQA DQA DQA DQA NC A2 NC NC 6 7 V DDQ NC NC DQB DQB V DDQ DQB DQB V DDQ DQA DQA V DDQ DQA DQA NC NC V DDQ 7 A B C D E F G H J K L M N P R T U
PIN DESCRIPTION
A0 A11 BA0-1 DQ CLK CKE DQM RAS CAS CE VDD VDDQ VSS Address Bus Bank Select Addresses Data Bus Clock Clock Enable Data Input/Output Mask Row Address Strobe Column Address Strobe Chip Enable Power Supply pins, 3.3V Data Bus Power Supply pins,3.3V Ground pins
*NOTE: Pin B3 is designated as NC/A12. This pin is used for future density upgrades as address pin A12.
June 2002, Rev. 1 ECO #15237 1 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
FIG. 2 8MX32 SDRAM BLOCK DIAGRAM
ADDR0-11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 BA0 BA1 DQMA DQMB CE RAS CAS WE CLK CKE BA0 BA1 LDQM UDQM CS RAS CAS WE CLK CKE DQ0-7 DQ8-15 DQA DQB
WED3DL328V
DQ0-31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 BA0 BA1 DQMC DQMD LDQM UDQM CS RAS CAS WE CLK CKE
DQ0-7 DQ8-15
DQC DQD
White Electronic Designs Corporation Westborough, MA (508) 366-5151
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White Electronic Designs
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CLK CKE CE RAS, CAS WE BA0,BA1 Type Input Input Input Input Input Signal Pulse Level Pulse Pulse Level Polarity Positive Edge Active High Active Low Active Low Function
WED3DL328V
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CE disable or enable device operation by masking or enabling all inputs except CLK, CKE and DQM. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-8 defines the column address (CA0-8) when sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged . If A10/AP is low, autoprecharge is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge.
A0-11, A10/AP
I nput
Level
DQ DQM
Input/Output Input
Level Pulse
Mask Active High
Data Input/Output are multiplexed on the same pins The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. Power and ground for the input buffers and the core logic. Isolated power and ground for the output buffers to improve noise immunity.
VDD, VSS VDDQ
Supply Supply
ABSOLUTE MAXIMUM RATINGS*
Parameter Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current Symbol VDD/VDDQ VIN VOUT T OPR T STG PD IOS Min -1.0 -1.0 -1.0 -0 -55 Max +4.6 +4.6 +4.6 +70 +125 1.5 50 Units V V V °C °C W mA
RECOMMENDED DC OPERATING CONDITIONS (Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C)
Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage (IOH = -2mA) Output Low Voltage (IOL = 2mA) Input Leakage Voltage Output Leakage Voltage Symbol VDD/VDDQ VIH VIL VOH VOL IIL IOL Min 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 3.0 Max 3.6 VDD +0.3 0.8 0.4 5 5 Unit V V V V V µA µA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25°C, f = 1MHz, VDD = 3.3V)
Parameter Input Capacitance Input/Output Capacitance (DQ) Symbol CI1 COut Max 4 5 Unit pF pF
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
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