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Details, datasheet, quote on part number:WED3DL644V
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| Part: | WED3DL644V |
| Category: | Memory => DRAM => SDR SDRAM => SDRAM MCP |
| Description: | Organization = 4Mx64 ;; Speed MHZ = 100-133 ;; Volt = 3.3 ;; Package = 153 Bga ;; Temp = C ;; |
| Company: | White Electronic Designs Corporation |
| Datasheet: | Download WED3DL644V datasheet File size : 1948 kB |
| Request For quote: | Find where to buy WED3DL644V
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Datasheet text preview:
White Electronic Designs
4Mx64 SDRAM
F E ATURES
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53% Space Savings vs. Monolithic Solution Reduced System Inductance and Capacitance 3.3V Operating Supply Voltage Fully Synchronous to Positive Clock Edge Clock Frequencies of 133, 125 and 100MHz Burst Operation Sequential or Interleaved Burst Length = Programmable 1, 2, 4, 8 or Full Page Burst Read and Write Multiple Burst Read and Single Write
WED3DL644V
DESCRIPTION
The WED3DL644V is a 4Mx64 Synchronous DRAM configured as 4x1Mx64. The SDRAM BGA is constructed with four 4Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 119 lead, 14mm by 22mm, BGA. The WED3DL644V is available in clock speeds of 133MHz, 125MHz and 100MHz. The range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The package and design provides performance enhancements via a 50% reduction in capacitance vs. four monolithic devices. The design includes internal ground and power planes which reduces inductance on the ground and power pins allowing for improved decoupling and a reduction in system noise.
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Data Mask Control Per Byte Auto and Self Refresh Automatic and Controlled Precharge Commands Suspend Mode and Power Down Mode 17mm x 23mm, 153 BGA
FIG. 1
PINOUT (TOP
A B C D E F G H J K L M N P R T U 1 D Q 41 D Q 40 D Q 33 D Q 32 NC NC CE2 NC NC NC CE1 NC NC D Q 30 D Q 31 D Q 22 D Q 23 2 3 D Q 43 D Q 45 D Q 42 D Q 44 D Q 35 D Q 37 D Q 34 D Q 36 DQML2 D Q M H2 VDDQ VDDQ CE3 VS S NC VS S CKE CAS NC VS S CE0 VS S VDDQ VDDQ D Q M H 1 DQML1 D Q 28 D Q 26 D Q 29 D Q 27 D Q 20 D Q 18 D Q 21 D Q 19 4 D Q 47 D Q 46 D Q 39 D Q 38 V DD V DD VS S CLK1 RAS CLK0 VS S V DD V DD D Q 24 D Q 25 D Q 16 D Q 17 5 NC NC NC NC V DD V DD VS S VS S WE VS S VS S V DD V DD NC NC NC NC VIEW) 6 D Q 48 D Q 49 D Q 56 D Q 57 VDD VDD VS S VS S A9 VS S VS S VDD VDD D Q 06 D Q 07 D Q 14 D Q 15 7 8 D Q 50 D Q 52 D Q 51 D Q 53 D Q 58 D Q 60 D Q 59 D Q 61 DQML3 D Q M H 3 VDDQ VDDQ VS S A4 VS S A5 A11 A6 VS S A7 VS S A8 VDDQ VDDQ D Q M H 0 DQML0 D Q 04 D Q 02 D Q 05 D Q 03 D Q 12 D Q 10 D Q 13 D Q 11 9 D Q 54 D Q 55 D Q 62 D Q 63 NC A3 A2 A1 A0 A10 BA 1 BA 0 NC D Q 00 D Q 01 D Q 08 D Q 09
PIN DESCRIPTION
A0 A11 Address Bus BA0-1 Bank Select Addresses D Q 0-63 Data Bus C L K 0-1 Clock CKE Clock Enable DQML0-3 Data Input/Output Masks D Q M H 0-3 RAS Row Address Strobe CAS Column Address Strobe WE Write Enable C E0 - 3 Chip Enables VDD Power Supply pins, 3.3V VDDQ Data Bus Power Supply, 3.3V VS S Ground pins
August 2002 Rev.1 ECO #15464
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
FIG. 2 4MX64 SDRAM BLOCK DIAGRAM
WED3DL644V
White Electronic Designs Corporation Westborough, MA (508) 366-5151
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White Electronic Designs
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CLK CKE Type Input Input Signal Polarity P u l s e P o s i t i v e Edge Level A c t i v e High
WED3DL644V
CE R A S , CAS WE BA0,BA1
Input Input Input
Pulse Pulse Level
A c t i v e Low A c t i v e Low
A0-11, A 1 0/ A P
Input
Level
DQ
DQML0 - (DQ0-7) DQMH0 - (DQ8-15) DQML1 - (DQ16-23) DQMH1 - (DQ24-31) DQML2 - (DQ31-39) DQMH2 - (DQ40-47) DQML3 - (DQ48-55) DQMH3 - (DQ56-63)
Input/Output L e v e l
Input
Pulse
Mask A c t i v e High
Function T h e system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. A c t i v a t e s the CLK signal when high and deactivates the CLK signal when low. By d e a c t i v a t i n g the clock, CKE low initiates the Power Down mode, Suspend mode, or the S e l f Refresh mode. C E disable or enable device operation by masking or enabling all inputs except CLK, C K E and DQM. W h e n sampled at the positive rising edge of the clock, CAS, RAS, and WE define the o p e r a t i o n to be executed by the SDRAM. S e l e c t s which SDRAM bank is to be active. During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge. D u r i n g a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the rising clock edge. In addition to the row address, A10/AP is used to invoke A u t o p r e c h a r g e operation at the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10/AP is low, a u t o p r e c h a r g e is disabled. During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0, BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge. D a t a Input/Output are multiplexed on the same pins T h e Data Input/Output mask places the DQ buffers in a high impedance state when s a m p l e d high. In Read mode, DQM has a latency of two clock cycles and controls the o u t p u t buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the W r i t e operation if DQM is high. Each DQM pin controls the byte in parentheses a s s o c i a t e d with it.
VD D, VSS
Supply
Power and ground.
A BSOLUTE MAXIMUM RATINGS
Parameter Symbol Power Supply Voltage VDD/VDDQ Input Voltage VIN Output Voltage VOUT Operating Temperature TOPR Storage Temperature T STG Power Dissipation PD Short Circuit Output Current IOS Min -1.0 -1.0 -1.0 -40 -55 Max +4.6 +4.6 +4.6 +85 +125 3.0 50 Units V V V °C °C W mA
RECOMMENDED DC OPERATING CONDITIONS (VOLTAGE REFERENCED TO: VSS = 0V)
Parameter Symbol Supply Voltage VDD/VDDQ Input High Voltage VIH Input Low Voltage VI L Output High Voltage (IOH =-2mA) VOH Output Low Voltage (IOL = 2mA) VOL Input Leakage Voltage IIL Output Leakage Voltage IOL Min Ty p Max Unit 3.0 3.3 3.6 V 2.0 3.0 VDD +0.3 V -0.3 0.8 V 2.4 V 0.4 V -5 5 µA -5 5 µA
Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25°C, f= 1MHZ, VDD = 3.3V)
Parameter I n p u t Capacitance I n p u t / O u t p u t Capacitance (DQ) Symbol CI N C OUT Max 8 5 Unit pF pF
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
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