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Details, datasheet, quote on part number:WF128K16-60
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| Part: | WF128K16-60 |
| Category: | Memory => Flash => Flash MCP |
| Description: | Organization = 128Kx16 ;; Speed (ns) = 60-120 ;; Volt = 5 ;; Package = 32 Dip ;; Temp = C,i,m ;; |
| Company: | White Electronic Designs Corporation |
| Datasheet: | Download WF128K16-60 datasheet File size : 190 kB |
| Request For quote: | Find where to buy WF128K16-60
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Datasheet text preview:
WF128K16, WF256K16-XCX5 5V FLASH MODULE
FEATURES
s Access Times of 50, 60, 70, 90, 120 and 150ns s 40 pin Ceramic DIP (Package 303) s Organized as 128Kx16 and 256Kx16 s Sector Architecture · 8 equal size sectors of 16KBytes each per chip · Any combination of sectors can be concurrently erased. Also supports full chip erase s 100,000 Erase/Program Cycles Minimum (0°C to 70°C) s Data Retention, 10 Years at 125°C s Commercial, Industrial and Military Temperature Ranges s 5 Volt Programming; 5V ±10% Supply s Low Power CMOS s Embedded Erase and Program Algorithms s TTL Compatible Inputs and CMOS Outputs s Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation s Page Program Operation and Internal Program Control Time
* This data sheet describes a product under development, not fully characterized, and is subject to change without notice. Note: Programming information available upon request.
PRELIMINARY *
FIG. 1
PIN CONFIGURATION AND BLOCK DIAGRAM TOP VIEW
CS2*/NC CS1 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE
PIN DESCRIPTION
VCC WE A16 A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A0-16 I / O 0-15 CS1-2 OE WE VCC GND
Address Inputs Data Input/Output Chip Selects Output Enable Write Enable +5.0V Power Ground
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BLOCK DIAGRAM FOR WF256K16-XCX5
I/O0-7 WE OE A0-16 I/O8-15
FLASH MODULES
* CS2 for 256Kx16 and NC for 128Kx16
BLOCK DIAGRAM FOR WF128K16-XCX5
I/O0-7 WE OE A0-16 I/O8-15
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
CS1 (1) CS2
(1)
CS1
NOTE: 1. CS1 and CS2 are used to select the lower and upper 128Kx16 of the device. CS1 and CS2 must not be enabled at the same time.
O c t o b e r 1998
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White Microelectronics · Phoenix, AZ · (602) 437-1520
WF128K16, WF256K16-XCX5
ABSOLUTE MAXIMUM RATINGS (1)
Parameter Operating Temperature Supply Voltage Range (VCC) Signal voltage range (any pin except A9) (2) Storage Temperature Range Lead Temperature (soldering, 10 seconds) Data Retention Mil Temp Endurance (write/erase cycles) Mil Temp A9 Voltage for sector protect (VID) (3) -55 to +125 -2.0 to +7.0 -2.0 to +7.0 -65 to +150 +300 10 years 10,000 cycles min. -2.0 to +14.0 V Unit °C V V °C °C Test OE capacitance WE capacitance CS capacitance I/O0-7 capacitance Address capacitance
CAPACITANCE (TA = 25°C)
Symbol C OE CW E C CS CI / O C AD Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VI/O = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz Max 50 50 30 30 50 Unit pF pF pF pF
pF
This parameter is guaranteed by design but not tested.
NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is VCC + 0.5V. During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns. 3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp. (Mil.) Operating Temp. (Ind.) A9 Voltage for Sector Protect Symbol V CC V IH V IL TA TA VID Min 4.5 2.0 -0.5 -55 -40 11.5 Max 5.5 V C C + 0.3 +0.8 +125 +85 12.5 Unit V V V °C °C V
DC CHARACTERISTICS - CMOS COMPATIBLE (VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter Input Leakage Current Output Leakage Current VCC Active Current for Read (1) Symbol I LI I LO ICC1 I CC2 I CC3 V OL V OH1 V OH2 V LKO Conditions V C C = 5.5, VIN = GND to VCC V C C = 5.5, VIN = GND to VCC CS = VIL, OE = VIH C S = VIL, OE = VIH V C C = 5.5, CS = VIH, f = 5MHz I O L = 12.0 mA, VCC = 4.5 I O H = -2.5 mA, VCC = 4.5 I O H = -100 µA, VCC = 4.5 0.85xVcc V C C -0.4 3.2 128K x 16 Min Max 10 10 70 100 6 0.45 0.85xVcc V C C -0.4 3.2 256K x 16 Min Max 10 10 80 110 8 0.45 µA µA mA mA mA V V V V Unit
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FLASH MODULES
V C C Active Current for Program o r Erase (2) V C C Standby Current O u t p u t Low Voltage O u t p u t High Voltage O u t p u t High Voltage L o w VCC Lock Out Voltage
NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. I CC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
White Microelectronics · Phoenix, AZ · (602) 437-1520
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WF128K16, WF256K16-XCX5
PRINCIPLES OF OPERATION
The following principles of operation of the WF128K16-XCX5 and WF256K16-XCX5 are applicable to each 128K x 8 memory chip inside the MCM. Programming of the device is accomplished by executing the program command sequence. The program algorithm, which is an internal algorithm, automatically times the program pulse widths and verifies proper cell margin. Sectors can be programmed and verified in less than 0.3 seconds. Erase is accomplished by executing the erase command sequence. The erase algorithm, which is internal, automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The entire memory is typically erased and verified in three seconds (including pre-programming).
WRITE
Device erasure and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy an addressable memory location. The register is a latch used to store the commands, along with address and data information needed to execute the command. The command register is written by bringing Write-Enable to a logic-low level (VIL), while Chip-Select is low and OE is at VIH. Addresses are latched on the falling edge of the Write-Enable while data is latched on the rising edge of the WE pulse. Standard microprocessor write timings are used. Refer to AC Program characteristics, Figures 4 and 7.
BUS OPERATIONS READ
The device has two control functions, both of which must be logically active, to obtain data at the outputs. Chip-Select (CS) is the power control and should be used for device selection. Output-Enable (OE) is the output control and should be used to gate data to the output pins. Figure 3 illustrates read timing waveforms.
OUTPUT DISABLE
With Output-Enable at a logic-high level (VIH), output from the device is disabled. Output pins are placed in a high impedance state.
STANDBY MODE
The device has two standby modes, a CMOS standby mode (CS input held at VCC + 0.5V), and a TTL standby mode (CS is held VIH). In the standby mode the outputs are in a high impedance state, independent of the OE input. If the device is deselected during erasure or programming, the device will draw active current until the operation is completed.
Operation Read Standby Output Disable Write Enable Sector Protect Verify Sector Protect
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FLASH MODULES
TABLE 1 - BUS OPERATIONS
CS L H L L L L OE L X H H V ID L WE H X H L L H A0 A0 X X A0 X L A1 A1 X X A1 X H A9 A9 X X A9 V ID V ID I/O D OUT HIGH Z HIGH Z D IN X Code
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White Microelectronics · Phoenix, AZ · (602) 437-1520
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