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Details, datasheet, quote on part number:W27C4096P-12
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Datasheet text preview:
Preliminary W27C4096 256K × 16 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27C4096 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 262144 × 16 bits that operates on a single 5 volt power supply. The W27C4096 provides an electrical chip erase function.
FEATURES
· High speed access time: · · · ·
120/150 nS (max.) Read operating current: 30 mA (max.) Erase/Programming operating current 30 mA (max.) Standby current: 100 µA (max.) Single 5V power supply
· +14V erase/+12V programming voltage · Fully static operation · All inputs and outputs directly TTL/CMOS
compatible
· Three-state outputs · Available packages: 40-pin 600 mil DIP, TSOP
and 44-pin PLCC
PIN CONFIGURATIONS
VPP CE Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 GND Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33
BLOCK DIAGRAM
VDD A17 A16 A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0
Q0 CE OE CONTROL OUTPUT BUFFER
. .
Q15
40-pin DIP
32 31 30 29 28 27 26 25 24 23 22 21
A0
. .
A17
DECODER
CORE ARRAY
Q 1 3 6 Q12 Q11 Q10 Q9 Q8 GND NC Q7 Q6 Q5 Q4 7 8 9 10 11 12 13 14 15 16 17 18 Q 3
Q 1 4 5
Q 1 5 4
/ C E
V p p 2
N C 1
V
C C
A 1 7
A 1 6 42
A 1 5 41
A 1 4 40 39 38 37 36 A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5
VCC GND VPP
3
44 43
44-pin PLCC
35 34 33 32 31 30 29
PIN DESCRIPTION
SYMBOL A0-A17
40 39 38 37 36 35 34
19 Q 2
20 21 Q 1
22
23 24 25 N C A 0
26 27 A 2 A 3
28
Q 0
/ O E
A 1
A 4
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program/Erase Supply Voltage Power Supply Ground No Connection Publication Release Date: March 1999 Revision A1
A9 A10 A11 A12 A13 A14 A15 A16 A17 VCC VPP CE Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40-pin TSOP
33 32 31 30 29 28 27 26 25 24 23 22 21
GND A8 A7 A6 A5 A4 A3 A2 A1 A0 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Q0-Q15 CE OE VPP VCC GND NC
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Preliminary W27C4096
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27C4096 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C4096 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 = VPE (14V), A0 low, and all other address pins low and data input pins high.
Erase Verify Mode
After an erase operation, all of the words in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE high, and OE low.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V), VCC = VCP (5V), CE low, OE high, the address pins equal the desired address, and the input pins equal the desired inputs.
Program Verify Mode
All of the words in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each word is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE high, OE low and VCC = VCP (5V).
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high , VPP = VPP/VPE (12V/14V), and VCC = 5V, erasing or programming of nontarget chips is inhibited, so that except for the CE and VPP, and VCC, the W27C4096 may have common inputs.
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Preliminary W27C4096
Standby Mode
The standby mode significantly reduces VCC current. This mode is entered when CE high , VPP = 5V, and VCC = 5V. In standby mode, all outputs are in a high impedance state, independent of OE.
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27C4096 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
TABLE OF OPERATING MODES
(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X = VIH or VIL)
MODE CE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Erase Erase Verify Erase Inhibit Product Identifier-manufacturer Product Identifier-device VIL VIL VIH VCC ±0.3V VIL VIH VIH VIL VIH VIH VIL VIL OE VIL VIH X X VIH VIL X VIH VIL X VIL VIL A0 X X X X X X X VIL X X VIL VIH
PINS A9 X X X X X X X VPE X X VHH VHH VCC VCC VCC VCC VCC VCP VCP VCP VCE VCE VCE VCC VCC VPP VCC VCC VCC VCC VPP VPP VPP VPE VPE VPE VCC VCC OUTPUTS DOUT High Z High Z High Z DIN DOUT High Z DIH DOUT High Z 00DA (Hex) 000D (Hex)
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Publication Release Date: March 1999 Revision A1
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