The is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized × 8 bits that operates on a single 5 volt power supply. The W27E010 provides an electrical chip erase function.

High speed access time: 45/55/70/90/120 nS (max.) Read operating current: 30 mA (typ.) Erase/Programming operating current: 1 mA (typ.) Standby current: 5 µA (typ.) Single 5V power supply

+14V erase/+12V programming voltage Fully static operation All inputs and outputs directly TTL/CMOS compatible Three-state outputs

DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program Enable Program/Erase Supply Voltage Power Supply Ground No Connection

Like conventional UVEPROMs, the W27E010 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings are met.

The erase operation is the only way to change data from to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27E010 uses electrical erasure. Generally, the chip can be erased within mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE CE = VIL, (0.8V or below but higher than GND), OE = VIH (2V or above but lower than VCC), A9 = VHH A0 = VIL, and all other address pins equal VIL and data input pins equal VIH. Pulsing PGM low starts the erase operation.

After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VPP = VPE CE = VIL, and OE = VIL, PGM = VIH.

Programming is performed exactly is in conventional UVEPROMs, and programming is the only way to change cell data from to "0." The program mode is entered when VPP is raised to VPP (12V), VCC = VCP CE = VIL, OE = VIH, the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing PGM low starts the programming operation.

All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP CE = VIL, OE = VIL, and PGM = VIH.

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE = VIH, erasing or programming of non-target chips is inhibited, so that except for the CE, the W27E010 may have common inputs.

The standby mode significantly reduces VCC current. This mode is entered when CE = VIH. In standby mode, all outputs are in a high impedance state, independent of OE and PGM.

Since EPROMs are often used in large memory arrays, the W27E010 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.

EPROM power switching characteristics require careful device decoupling. System designers are concerned with three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have 0.1 µF ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

MODE CE Read Output Disable Standby (TTL) Standby (CMOS) Program Verify Program Inhibit Erase Verify Erase Inhibit Product IdentifierManufacturer Product Identifier-Device VIL VIH VCC ±0.3V VIL VIH VIL VIH VIL OE VIL VIH X VIH VIL X VIH VIL X VIL PGM VIL VIH X VIL VIH X

PINS A0 VIL X VIL VIH A9 VPE X VHH VCC VCP VCC VCP VCC VPP VCC VPP VPE VCC OUTPUTS DOUT High Z High Z High Z DIN DOUT High Z FF (Hex) DOUT High Z DA (Hex) 01 (Hex)