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Details, datasheet, quote on part number:W78C58F-16
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Datasheet text preview:
W78C58 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78C58 is a derivative of the W78C52 microcontroller family that provides extended internal ROM. The chip has 32K bytes of mask ROM and 256 bytes of RAM. This device provides an enhanced architecture that makes it more powerful and suitable for a variety of applications for general control systems. It provides on-chip 32KB mask ROM to accommodate large program codes, 256-bytes of non-volatile on-chip RAM, four 8-bit I/O ports, one 4-bit I/O port, three 16-bit timer/counters, eight sources with two-level interrupt structures, and on-chip oscillator clock circuits.
FEATURES
· DC to 40 MHz extensive operating frequency · 256-byte on-chip scratch pad RAM · 32K-byte on-chip mask ROM · 64K-byte address space for external Program Memory · 64K-byte address space for external Data Memory · Three 16-bit timer/counters · Four 8-bit bit-addressable I/O ports · One extra 4-bit bit-addressable I/O port, additonal INT2 / INT3
(Available on 44-pin PLCC/QFP package)
· Eight-source, two priority-level interrupts · Low EMI emission mode · Built-in programmable power-saving modes - Idle mode & Power-down mode · Packages:
- DIP 40: W78C58-16/24/40 - PLCC 44: W78C58P-16/24/40 - QFP 44: W78C58F-16/24/40 - TQFP 44: W78C58M-16/24/40
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Publication Release Date: December 1997 Revision A5
W78C58
PIN CONFIGURATIONS
40-Pin DIP (W78C58)
T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8
44-Pin PLCC (W78C58P)
/ I N T 3 , P 4V .C 2C
44-Pin QFP/TQFP (W78C58F/W78C58M)
T 2 E X , PPPP 1111 .... 4321 / I N TT 23 ,, PP 14V ..C 02C
T 2 E X , PPPP 1111 .... 4321
T 2 , P 1 . 0
A D 0 , P 0 . 0
A D 1 , P 0 . 1
A D 2 , P 0 . 2
A D 3 , P 0 . 3
A D 0 , P 0 . 0
A D 1 , P 0 . 1
A D 2 , P 0 . 2
A D 3 , P 0 . 3
P1.5 P1.6 P1.7 RST RXD, P3. INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPPP TS422 AS. . . L 001 1 ,, AA 89 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5
44 43 42 41 40 39 38 37 36 35 34 1 33 32 2 31 3 30 4 29 5 28 6 27 7 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPP TS42 AS.. L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
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W78C58
PIN DESCRIPTION
SYMBOL EA TYPE I DESCRIPTIONS EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. The ROM address and data will not be present on the bus if the EA pin is high and the program counter is within the 32 KB area. Otherwise they will be present on the bus. PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin. ALE OH ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. An ALE pulse is omitted during external data memory accesses. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: Ground potential. POWER SUPPLY: Supply voltage for operation. PORT 0: Function is the same as that of the standard 8052. PORT 1: Function is the same as that of the standard 8052. PORT 2: Function is the same as that of the standard 8052. PORT 3: Function is the same as that of the standard 8052. PORT 4: A 4-bit bi-directional parallel port and bit-addressable with internal pull-ups. Pin P4.3 and P4.2 have alternative function as external interrupt (INT2/INT3) source input. External interrupt 2: An extra interrupt input source. It cascades to pin P4.3 internally. External interrupt 3: An extra interrupt input source. It cascades to pin P4.2 internally.
PSEN
OH
RST XTAL1 XTAL2 VSS VDD P0.0-P0.7 P1.0-P1.7 P2.0-P2.7 P3.0-P3.7 P4.0-P4.3
IL I O I I I/O D I/O H I/O H I/O H I/O H
INT2 (P4.3) INT3 (P4.2)
IH IH
* Note : TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
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Publication Release Date: December 1997 Revision A5
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