The an 8-bit microcontroller which has an in-system programmable MTP-ROM for firmware updating. The instruction set of the W78E62B is fully compatible with the standard 8052. The W78E62B contains a 64K bytes of main MTP-ROM and a 4K bytes of auxiliary MTP-ROM which allows the contents of the 64KB main MTP-ROM to be updated by the loader program located at the 4KB auxiliary MTP-ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the MTP-ROM inside the W78E62B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78E62B microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.
Fully static design 8-bit CMOS microcontroller to 40 MHz. 64K bytes of in-system programmable MTP-ROM for Application Program (APROM). 4K bytes of auxiliary MTP-ROM for Loader Program (LDROM). Low standby current at full supply voltage. 512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable) 64K bytes program memory address space and 64K bytes data memory address space. Four 8-bit bi-directional ports. One 4-bit multipurpose programmable port. Build-in 74373 and 74244 logical functions on Port 2.(software programmable) Three 16-bit timer/counters One full duplex serial port Eight-sources, two-level interrupt capability Built-in power management Code protection PACKAGE - PLCC W78E62BP-40 - LQFP 48: W78E62BD-40
SYMBOL EA TYPE I DESCRIPTIONS EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the external ROM. The ROM address and data will not be presented on the bus if the EA pin is high and the program counter is within the 64 KB area. PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin. ALE O H ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs 1/6th of the oscillator frequency. An ALE pulse is omitted during external data memory accesses. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: ground potential. POWER SUPPLY: Supply voltage for operation. PORT 0: Function is the same as that of standard 8052. PORT 1: Function is the same as that of standard 8052. PORT 2: Port is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. It also can be programmed be an output-latched port like an on-chip or a buffer input port like an on-chip 74244. PORT 3: Function is the same as that of the standard 8052. PORT 4: A bi-directional I/O port with alternate function. See details below.
* Note : TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
Port 4 Port 4, SFR P4 at address a 4-bit multipurpose programmable I/O port. Each bit can be configured individually by software. The Port 4 has four different operation mode: In mode is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as external interrupt INT3 and INT2 if enabled. In mode 1, P4.0-P4.3 are read data strobe signals which are synchronized with RD signal at specified addresses. These signals can be used as chip-select signals for external peripherals.