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Details, datasheet, quote on part number:W83977EF
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| Part: | W83977EF |
| Category: | Interface and Interconnect |
| Description: | Description = W83877TF Plus Kbc, GP I/O, Wake-Up, Power Fail Resume ;; Package = QFP 128 |
| Company: | Winbond Electronics Corp America |
| Datasheet: | Download W83977EF datasheet File size : 754 kB |
| Request For quote: | Find where to buy W83977EF
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Datasheet text preview:
W83977EF WINBOND I/O
W83977EF Data Sheet Revision History
Version on Web
Pages 1 2 3 4 5 6 7 8 9 10 P86~P110 n.a. 4,7,49,50,53,55, 90,91 n.a.
Dates 06/01/98 06/16/98 12/30/03 03/07/03 04/25/03
Version 0.40 0.41 0.5 1.0 1.1
Main Contents First published. For Beta Site customers only Data correction Remove W83977CTF Part Update the new version on web Add Chapter 10 Configuration Register
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
W83977EF TABLE OF CONTENTS
GENERAL DESCRIPTION ............ 1 FEATURES ............ 2 PIN CONFIGURATION ......... 5 1.0 PIN DESCRIPTION........ 6 1.1 HOST INTERFACE ........... 6 1.2 GENERAL PURPOSE I/O PORT .......... 8 1.3 SERIAL PORT INTERFACE......... 9 1.4 INFRARED INTERFACE............ 10 1.5 MULTI-MODE PARALLEL PORT ........ 11 1.6 FDC INTERFACE .......... 16 1.7 KBC INTERFACE .......... 18 1.8 POWER PINS ............ 18 1.9 ACPI INTERFACE ......... 18 2.0 FDC FUNCTIONAL DESCRIPTION..... 19 2.1 W83977EF FDC ........ 19 2.1.1 AT interface ......... 19 2.1.2 FIFO (Data) ......... 19 2.1.3 Data Separator.... 20 2.1.4 Write Precompensation......... 20 2.1.5 Perpendicular Recording Mode ........... 21 2.1.5 Perpendicular Recording Mode ........... 21 2.1.6 FDC Core ............ 21 2.1.7 FDC Commands .......... 21 2.2 REGISTER DESCRIPTIONS...... 33 2.2.1 Status Register A (SA Register) (Read base address + 0) ........ 33 2.2.2 Status Register B (SB Register) (Read base address + 1) ........ 35 2.2.3 Digital Output Register (DO Register) (Write base address + 2)......... 37 2.2.4 Tape Drive Register (TD Register) (Read base address + 3) .... 37 2.2.5 Main Status Register (MS Register) (Read base address + 4) ........... 38 2.2.6 Data Rate Register (DR Register) (Write base address + 4) ..... 38 2.2.7 FIFO Register (R/W base address + 5) ........ 40 2.2.8 Digital Input Register (DI Register) (Read base address + 7) .... 42 2.2.9 Configuration Control Register (CC Register) (Write base address + 7) ..... 43 3.0 UART PORT... 45 3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ... 45 3.2 REGISTER ADDRESS .... 45 3.2.1 UART Control Register (UCR) (Read/Write) ...... 45 3.2.2 UART Status Register (USR) (Read/Write) ........ 48 3.2.3 Handshake Control Register (HCR) (Read/Write)....... 48 Publication Release Date: April 2003 Revision 1.1
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