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Details, datasheet, quote on part number:W981216AH
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Datasheet text preview:
W981216AH 2M x 16 bit x 4 Banks SDRAM
Features
· · · · · · · · · · · · · 3.3Vą0.3V power supply Up to 133 MHz clock frequency 2,097,152 words x 4 banks x 16 bits organization Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8 , and full page Burst read, Single Writes Mode Byte data controlled by UDQM and LDQM Power-Down Mode Auto-Precharge and controlled precharge 4k refresh cycles / 64ms Interface: LVTTL Package: TSOP II 54 pin, 400 mil - 0.80
General Description
W981216AH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 2M words x 4 banks x 16 bits. Using pipelined architecture and 0.20um process technology, W981216AH delivers a data bandwidth of up to 266M bytes per second (-75). To fully comply to the personal computer industrial standard, W981216AH is sorted into two speed grades: -75 and -8H. The -75 is compliant to the PC133/CL3 specification, the 8H is compliant to PC100/CL2 specification. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counrter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst legnth, latency cycle, interleave or sequential burst to maximize its performance. W981216AH is ideal for main memory in high performance applications.
Key Parameters
Symbol tCK tAC tRP tRCD ICC1 ICC4 ICC6 Description Clock Cycle Time Access Time from CLK Precharge to Active Command Active to Read/Write Command Operation Current ( Single bank ) Burst Operation Current Self-Refresh Current min/max min max min min max max max -75 (PC133) 7.5ns 5.4ns 20ns 20ns 85mA 120mA 2mA -8H (PC100) 8ns 6ns 20ns 20ns 80mA 110mA 2mA
Revision 1.0 -1-
Publication Release Date: March, 1999
W981216AH 2M x 16 bit x 4 Banks SDRAM
BLOCK DIAGRAM
CLK CLOCK BUFFER CKE
CS RAS CAS DECODER
CONTROL SIGNAL GENERATOR
COMMAND
COLUMN DECODER WE ROW DECODER ROW DECODER
COLUMN DECODER
A10
CELL ARRAY BANK #0
CELL ARRAY BANK #1
A0 ADDRESS BUFFER A9 A11 BS0 BS1
MODE REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
DMn
DATA CONTROL CIRCUIT
DQ BUFFER
DQ0 DQ15
REFRESH COUNTER
COLUMN COUNTER
UDQM LDQM
COLUMN DECODER ROW DECODER ROW DECODER
COLUMN DECODER
CELL ARRAY BANK #2
CELL ARRAY BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The cell array configuration is 4096 * 512 * 16.
Revision 1.0 -2-
Publication Release Date: March, 1999
W981216AH 2M x 16 bit x 4 Banks SDRAM
Pin Assignment
Pin Number 23 ~ 26, 22, 29 ~35 20, 21 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 19 Pin Name A0~ A11 BS0, BS1 DQ0 ~ DQ15 Function Address Bank Select Data Input/ Output Description Multiplexed pins for row and column address. Row address : A0 ~ A11. Column address: A0 ~ A8. Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input.
CS#
Chip Select
18 17 16 39, 15
RAS# CAS# WE# UDQM/ LDQM CLK CKE
Row Address Strobe Column Address Strobe Write Enable input/output mask Clock Inputs Clock Enable
Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock, RAS#, CAS# and WE# define the operation to be executed. Referred to RAS# Referred to RAS# The output buffer is placed at Hi-Z(with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Separated power from VCC, used for output buffers to improve noise. Separated ground from VSS, used for output buffers to improve noise. No connection
38 37
1, 14, 27 28, 41, 54 3, 9, 43, 49 6, 12, 46, 52 36, 40
VCC VSS VCCQ VSSQ NC
Power ( +3.3 V ) Ground Power ( + 3.3 V ) for I/O buffer Ground for I/O buffer No Connection
Revision 1.0 -3-
Publication Release Date: March, 1999
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