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Details, datasheet, quote on part number:WM8148
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| Part: | WM8148 |
| Category: | Sensors => Image Sensors => CDD and CIS |
| Description: | WM8148 : 12-BIT/12 MSPS Ccd/cis Analogue Front End/digitiser |
| Company: | Wolfson Microelectronics Ltd. |
| Datasheet: | Download WM8148 datasheet File size : 503 kB |
| Request For quote: | Find where to buy WM8148
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Datasheet text preview:
WM8148 12-bit/12MSPS CCD/CIS Analogue Front End/Digitiser
Production Data, April 1999, Rev 4.0
DESCRIPTION
The WM8148 is a 12-bit, 12MSPS analogue front end/ digitiser IC, which interfaces to colour or monochrome linear array CCDs or contact image sensors (CIS). The device includes all the signal conditioning circuitry required to process the analogue signals from the CCD or CIS prior to the internal ADC. Three signal-processing channels are included in the device. Each channel features reset level clamping, correlated double sampling (CDS), offset correction and programmable gain amplification (PGA). The output signal from each channel is then multiplexed into a high performance 12-bit analogue to digital converter (ADC). The reset level clamp and/or CDS functions can be selected or bypassed depending on the application. The WM8148 can be operated in several modes. The operational mode of the device, including the sampling scheme and power management is programmed via the serial/parallel control interface. Output data is presented in either 12-bit parallel or bytewide (8+4-bit) format.
FEATURES
· · · · · · · · · · · Correlated double sampling Programmable gain amplifier Programmable input clamp voltage Offset correction 12-bit, 12MSPS ADC Internal voltage reference 12-bit or 8+4 bit data output mode Single 5V supply or 5V analogue/3.3V digital supply Programmable sample timing Control interface compatible with previous Wolfson AFEs 48-pin TQFP package
APPLICATIONS
· · · · · · · Flatbed scanners Document scanners Multi-function peripherals (MFPs) Colour copiers Character recognition systems Linear array CCDs Contact image sensors (CIS)
BLOCK DIAGRAM
RLC (2) MCLK VSMP (5) (7) A V D D 1- 4 (41,28,27,3) DVDD1-2 (1,13) VRX VRB VRT (32) (29) (31)
C L R S VS
T I M I N G CONTROL
VREF/BIAS
WM8148
R I N P (36)
CDS RLC 8 OFFSET DAC
+
PGA ± FULL . _ S C A L E .2
+
( 4 3 ) OEB
6
G I N P (37)
CDS RLC 8 OFFSET DAC
+
PGA ± FULL . _ S C A L E .2
+
MUX
12-BIT ADC
12/8 BIT MUX
OP[11:0] (9-12,14-21)
6
B I N P (39)
CDS RLC 8 OFFSET DAC
+
PGA ± FULL . _ S C A L E .2
+
(48) (34) (45) (46) (47) (42) (44) PNS OVRD SDI/DNA SCK/RNW SEN/STB NRESET SDO
6
V R L C (33)
RLC DAC 4
CONFIGURABLE SERIAL/PARALLEL C O N T R O L INTERFACE
(35,40,30,25,6) AGND1 - 5
(8,24,4,26) DGND1 - 4
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Production Data contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions.
©1999 Wolfson Microelectronics Ltd.
WM8148 PIN CONFIGURATION
SCK/RNW SDI/DNA SEN/STB NRESET AGND2 BINP AVDD1 NC GINP
Production Data
ORDERING INFORMATION
DEVICE XW M8148CFT/V TEMP. RANGE 0 to 70 C
o
PACKAGE 48-pin 1mm thick body TQFP
SDO
DVDD1 RLC AVDD4 DGND3 MCLK AGND5 VSMP DGND1 OP0 OP1 OP2 OP3
1 2 3 4 5 6 7 8 9
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
OEB
PNS
RINP AGND1 OVRD VRLC VRX VRT AGND3 VRB AVDD2 AVDD3 DGND4 AGND4
10 11
25 12 13 14 15 16 17 18 19 20 21 22 23 24
PIN DESCRIPTION
PIN 1 2 3 4 5 NAME DVDD1 RLC AVDD4 DGND3 MCLK TYPE Supply Digital input Supply Ground Digital input DESCRIPTION Digital supply (3.3V to 5V) for digital inputs and SDO. Selects whether reset level clamp is applied, active high. If RLC is required on every pixel then this pin can be tied high. Analogue supply (5V). Digital ground (0V). Master clock. This clock is applied at N times the input pixel rate (N = 12, 8, 6, or 4 dependent on input sampling mode). MCLK is divided internally by N to generate internal clocks and to provide the clock source for digital logic. Analogue ground (0V). Video sample synchronisation pulse. This pin may be either an input (default) or output. Input: This signal is pulsed externally to synchronise the WM8148's video input sample instant and the N-phase internal clock to CCD clocks and interface bus timing. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DGND1 OP0 OP1 OP2 OP3 DVDD2 OP4 OP5 OP6 OP7 OP8 OP9 OP10 OP11 Ground Digital output Digital output Digital output Digital output Supply Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Output: This signal is pulsed internally to flag the video input sample instant, to allow the CCD clocks and interface bus to be synchronised to the WM8148.
6 7
AGND5 VSMP
Ground Digital IO
WOLFSON MICROELECTRONICS LTD
NC NC DGND2
OP10
DVDD2
OP11
OP4 OP5 OP6
OP7 OP8
OP9
Digital ground (0V) for output drivers. 12-bit signal data output bus. Data is output MSB on OP[11] and LSB on pin OP[0]. See description of pins 14-21 for mode definitions.
Digital supply (3.3V-5V) for Digital IO pins and OP0 to OP3 12-bit bi-directional data bus. On pins OP[4] to OP[11], signal data is output if OEB = 0 and register write data is input if OEB = 1. There are five main modes: · Hi-Z: when OEB = 1 · Output 12-bit: twelve bit signal data output from bus · Output 8-bit muxed: signal data output on OP[11:4] at 2 ADC conversion rate · Input 8-bit: register write data input on OP[11:4] · Output 8-bit: register readback data output on OP[11:4]
PD Rev 4.0 April 1999
2
WM8148
PIN 22 23 24 25 26 27 28 29 30 31 32 33 NAME NC NC DGND2 AGND4 DGND4 AVDD3 AVDD2 VRB AGND3 VRT VRX VRLC Ground Ground Ground Supply Supply Analogue output Ground Analogue output Analogue output Analogue IO TYPE DESCRIPTION No internal connection. No internal connection. Digital ground (0V) for output drivers. Analogue ground (0V). Digital ground (0V). Analogue supply (5V). Analogue supply (5V).
Production Data
Lower reference voltage. This pin must be connected to AGND and VRT via decoupling capacitors. See Recommended External Components section for details. Analogue ground (0V). Upper reference voltage. This pin must be connected to AGND and VRB via decoupling capacitors. See Recommended External Components section for details. Input return bias voltage. This pin must be connected to AGND via decoupling capacitors. See Recommended External Components section for details. Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. See Recommended External Components section for details. VRLC can be externally driven if programmed Hi-Z. Override pin. Typically tied low externally. The sense of this pin defines the device function on reset. Refer to the description of pin 42 for details. Analogue ground (0V). Red channel input video. Green channel input video. No internal connection. Blue channel input video. Analogue ground (0V). Analogue supply (5V). Reset input, active low. This signal forces a reset of all internal registers. Registers are set to defaults if pin OVRD is tied low. If pin OVRD is tied high then all registers are set to defaults except EN which is set to 1 and RLCEXT which is set to 0. This will turn on all analogue circuitry including the RLC DAC buffers driving the VRLC pin. Output enable control, all outputs disabled when OEB = 1. This pin must be externally connected. Serial Interface: register read-back, VSMP output, setup error flag or over-range flag (depending on control bits SDO [1:0]). Serial interface: serial input data signal. Serial interface: serial clock signal. Parallel Interface: Hi-Z, VSMP output, set-up error flag or over-range flag (depending on control bits SDO [1:0]). Parallel interface: High = data, Low = address. Parallel interface: High = OP[11:4] is output bus, Low = OP[11:4] is input bus (Hi-Z). Parallel interface: strobe, active low.
34
OVRD
Analogue input
35 36 37 38 39 40 41 42
AGND1 RINP GINP NC BINP AGND2 AVDD1 NRESET
Ground Analogue input Analogue input Analogue input Ground Supply Digital input
43 44
OEB SDO
Digital input Digital output
45 46
SDI/DNA SCK/RNW
Digital input Digital input
47 48
SEN/STB PNS
Digital input Digital input
Serial interface: enable pulse, active high.
Low = serial interface, High = parallel interface. This pin must be externally connected.
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
3
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