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Details, datasheet, quote on part number:X1203
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| Part: | X1203 |
| Category: | Timing Circuits => Clock Circuits |
| Description: | Real Time Clock/calendar With Dual Alarms And I2c Serial Interface |
| Company: | Xicor, Inc. |
| Datasheet: | Download X1203 datasheet File size : 160 kB |
| Request For quote: | Find where to buy X1203
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Datasheet text preview:
X1203
Real Time Clock/Calendar/Alarm
FEATURES ˇ 2 alarms--interrupt output -- Settable on the second, minute, hour, day, month, or day of the week -- Repeat alarm for time base generation ˇ 2-wire interface interoperable with I2C -- 400kHz data transfer rate ˇ Secondary power supply input with internal switch-over circuitry ˇ Low power CMOS -- <1ľA operating current -- <3mA active current during program -- <400ľA active current during data read ˇ Typical nonvolatile write cycle time: 5ms ˇ High reliability ˇ Small package options -- 8-lead SOIC package, 8-lead TSSOP package DESCRIPTION
2-WireTM RTC
The X1203 is a Real Time Clock with clock/calendar circuits and two alarms. The dual port clock and alarm registers allow the clock to operate, without loss of accuracy, even during read and write operations. The clock/calendar provides functionality that is controllable and readable through a set of registers. The clock, using a low cost 32.768kHz crystal input, accurately tracks the time in seconds, minutes, hours, date, day, month and years. It has leap year correction, automatic adjustment for the year 2000 and months with less than 31 days. An alarm match of the RTC sets an interrupt flag and activates an interrupt pin. An alternative alarm function provides a pulsed interrupt for long time constant timebases. The device offers a backup power input pin. This VBACK pin allows the device to be backed up by a nonrechargeable battery. The RTC is fully operational from 2.7 to 5.5 Volts and the RTC portion of the X1203 device remains fully operational down to 1.8 Volts.
BLOCK DIAGRAM
X1 Oscillator X2 Frequency Divider 1Hz Timer Calendar Logic
32.768kHz
Time Keeping Registers (SRAM)
Mask 8 Interrupt Enable Alarm
SCL SDA
Serial Interface Decoder
Control Decode Logic
Control Registers (EEPROM)
Status Registers (SRAM)
Alarm
Compare Alarm Regs (EEPROM)
IRQ
REV 1.2.0 2/13/01
James Tsang
www.xicor.com
Characteristics subject to change without notice.
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X1203
PIN CONFIGURATION
X1203 8-Pin SOIC X1 X2 IRQ VSS 1 2 3 4 8 7 6 5 VCC VBACK SCL SDA
on-chip oscillator. The crystal supplies a timebase for a clock/oscillator, see figure 1. Using an external timebase, the internal clock is driven by the external signal on X1, with X2 left unconnected. Figure 1. Recommended Crystal Connection
12pF X1 X2
X1203 8-Pin TSSOP VBACK VCC X1 X2 1 2 3 4 8 7 6 5 SCL SDA VSS IRQ 68pF
10M 360K
POWER CONTROL OPERATION The Power control circuit accepts a VCC and a VBACK input. The power control circuit will switch to VBACK when VCC < VBACK 0.2V. It will switch back to VCC when VCC exceeds VBACK. Figure 2. Power Control
VCC VBACK VCC = VBACK -0.2V Internal Voltage
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not gated). Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated). An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pulldown. The circuit is designed for 400kHz 2-wire interface speeds. VBACK This input provides a backup supply voltage to the device. VBACK supplies power to the device in the event the VCC supply fails. Interrupt Output - IRQ This is an interrupt signal output. This signal notifies a host processor that alarm has occurred and requests action. It is an open drain active LOW output. X1, X2 The X1 and X2 pins are the input and output, respectively, of an inverting amplifier that can accept an external 32.768kHz square wave reference on X1 or can be configured for use as an on-chip oscillator. A 32.768kHz quartz crystal such as a Citizen CFS-206 is used with the
REV 1.2.0 2/13/01
REAL TIME CLOCK OPERATION The Real Time Clock (RTC) uses an external 32.768kHz quar tz crystal network or timebase to maintain an accurate internal representation of the year, month, day, date, hour, minute, and seconds. The RTC has leap-year correction and a century byte. The clock will also correct for months having fewer than 31 days and will have a bit that controls 24-hour or AM/PM format. After power up, when both VCC and VBACK fail, the clock will not advance unless at least one byte is written to the RTC register. Reading the Real Time Clock The RTC is read by initiating a read command and specifying the address corresponding to the register of the real time clock. The RTC registers can then be read in a sequential read mode. Since the clock runs continuously and a read takes a finite amount of time, there is the possibility that the clock could change during the
Characteristics subject to change without notice.
www.xicor.com
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X1203
course of a read operation. In this device, the time is latched by the read command (falling edge of the clock on the ACK bit prior to RTC data output) into a separate latch to avoid time changes during the read operation. The clock continues to run. Alarms occurring during a read are unaffected by the read operation. Writing to the Real Time Clock The time and date may be set by writing to the RTC registers. To avoid changing the current time by an incomplete write operation, the current time value is loaded into a separate buffer at the falling edge of the clock on the ACK bit before the RTC data input bytes, the clock continues to run. The new serial input data replaces the values in the buffer. This new RTC value is loaded back into the RTC register by a stop bit at the end of a valid write sequence. An invalid write operation aborts the time update procedure and the contents of the buffer are discarded. After a valid write operation the RTC will reflect the newly loaded data beginning with the first "one second" clock cycle after the stop bit. The RTC continues to update the time while an RTC register write is in progress and the RTC continues to run during any nonvolatile write sequences. A single byte may be written to the RTC without affecting the other bytes. CLOCK/CONTROL REGISTERS (CCR) The Control/Clock Registers are located in an area logically separated from the array and are only accessible following a slave byte of "1101111x" and reads or writes to addresses [0000h:003Fh]. CCR Access The contents of the CCR can be modified by performing a byte or a page write operation directly to any address in the CCR. Prior to writing to the CCR (except the status register), however, the WEL and RWEL bits must be set using a two step process (See section "Writing to the Clock/Control Registers.") The CCR is divided into 5 sections. These are: 1. Alarm 0 (8 bytes) 2. Alarm 1 (8 bytes) 3. Control (1 byte) 4. Real Time Clock (8 bytes) 5. Status (1 byte) Sections 1) through 3) are nonvolatile and Sections 4) and 5) are volatile. Each register is read and written through buffers. The non volatile portion (or the counter por tion of the RTC) is updated only if RWEL is set and after a valid write operation and stop bit. A sequential read or page write operation provides access to the contents of only one section of the CCR per operation. Access to another section requires a new operation. Continued reads or writes, once reaching the end of a section, will wrap around to the start of the section. A read or page write can begin at any address in the CCR. Section 5) is a volatile register. It is not necessary to set the RWEL bit prior to writing the status register. Section 5) supports a single byte read or write only. Continued reads or writes from this section terminates the operation. The state of the CCR can be read by performing a random read at any address in the CCR at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. The read instruction latches all Clock registers into a buffer, so an update of the clock does not change the time being read. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read of the CCR, the address remains at the previous address +1 so the user can execute a current address read of the CCR and continue reading the next register. ALARM REGISTERS There are two alarm registers whose contents mimic the contents of the RTC register, but add enable bits and exclude the 24-hour time selection bit. The enable bits specify which registers to use in the comparison between the alarm and real time registers. For example: The user can set the X1203 to alarm every Wednesday at 8:00AM by setting the EDWn, the EHRn and EMNn enable bits to `1' and setting the DWAn, HRAn and MNAn Alarm registers to 8:00AM Wednesday. A daily alarm for 9:30PM results when the EHRn and EMNn enable bits are set to `1' and the HRAn and MNAn registers set 9:30PM. Setting the EMOn bit in combination with other enable bits and a specific alarm time, the user can establish an alarm that triggers at the same time once a year.
REV 1.2.0 2/13/01
www.xicor.com
Characteristics subject to change without notice.
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