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Details, datasheet, quote on part number:X20C17P-45
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Datasheet text preview:
APPLICATION NOTE
AVAILABL E
X20C17 16K
AN56
X20C17
High Speed AUTOSTORETM NOVRAM
2K x 8 Bit
FEATURES
DESCRIPTION
The Xicor X20C17 is a 2K x 8 NOVRAM featuring a highspeed static RAM overlaid bit-for-bit with a nonvolatile e l e c t r i c a l l y erasable PROM (E 2 P R O M ) and the AUTOSTORE feature which automatically saves the RAM contents to E2PROM at power-down. The X20C17 is fabricated with advanced CMOS floating gate technology to achieve high speed with low power and wide power-supply margin. The X20C17 features a compatible JEDEC approved byte-wide memory pinout for industry standard SRAMs. The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 2.5ms or less. An automatic array recall operation reloads the contents of the E2PROM into RAM upon power-up. Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years.
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24-Pin Standard SRAM DIP Pinout Fast Access Time: 35ns, 45ns, 55ns High Reliability -- Endurance: 1,000,000 Nonvolatile Store Operations -- Retention: 100 Years Minimum AUTOSTORETM NOVRAM -- Automatically Stores SRAM Data Into the E2PROM Array When VCC Low Threshold is Detected -- E2PROM Data Automatically Recalled Into RAM Upon Power-up Low Power CMOS -- Standby: 250µA Infinite E2PROM Array Recall, and RAM Read and Write Cycles
PIN CONFIGURATION
PLASTIC A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 X20C17 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
2015 ILL F02.1
AUTOSTORETM NOVRAM is a trademark of Xicor, Inc. ©Xicor, Inc. 1992, 1995 Patents Pending 2015-2.5 8/1/97 T1/C0/D0 SH
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Characteristics subject to change without notice
X20C17
PIN DESCRIPTIONS Addresses (A0A10) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE. Data In/Data Out (I/O0I/O7) Data is written to or read from the X20C17 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH. Write Enable (WE) The Write Enable input controls the writing of data to the static RAM. FUNCTIONAL DIAGRAM PIN NAMES Symbol A0A10 I/O0I/O7 WE CE OE VCC VSS Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground
2015 PGM T01
VCC SENSE EEPROM ARRAY
AL L
A3A8
ROW SELECT
CE OE WE CONTROL LOGIC
A0A2 A9A10
COLUMN SELECT & I/OS
I/O0I/O7
ST O
HIGH SPEED 2K x 8 SRAM ARRAY
R R E
EC
2015 FHD F01.1
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X20C17
DEVICE OPERATION The CE, OE, and WE inputs control the X20C17 operat i o n . The X20C17 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH. RAM Operations RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW. A write operation requires CE and WE to be LOW. There is no limit to the number of read or write operations performed to the RAM portion of the X20C17. Memory Transfer Operations There are two memory transfer operations: a recall operation whereby the data stored in the E2PROM array is transferred to the RAM array; and a store operation which causes the entire contents of the RAM array to be stored in the E2PROM array. Recall operations are performed automatically upon power-up. Store operations are performed automatically upon power-down. The store operation take a maximum of 2.5ms. Write Protection The X20C17 supports two methods of protecting the nonvolatile data. --If after power-up no RAM write operations have occured, no AUTOSTORE operation can be initiated. --VCC Sense All functions are inhibited when VCC is 3V typical.
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
SYMBOL TABLE The following symbol table provides a key to understanding the conventions used in the device timing diagrams. The diagrams should be used in conjunction with the device timing specifications to determine actual device operation and performance, as well as device suitability for user's application.
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