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Details, datasheet, quote on part number:X24026Y
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Datasheet text preview:
ISO 7816 Compatible 2K
X24026
Serial E2PROM
DESCRIPTION
256 x 8 Bit
FEATURES ˇ 2.7V to 5.5V Power Supply ˇ Low Power CMOS -- Active Current Less Than 1mA -- Standby Current Less Than 50ľA ˇ Internally Organized 256 x 8 ˇ Self Timed Write Cycle -- Typical Write Cycle Time of 5 ms ˇ 2 Wire Serial Interface -- Bidirectional Data Transfer Protocol ˇ Four Byte Page Write Operation -- Minimizes Total Write Time Per Byte ˇ High Reliability -- Endurance: 100,000 Cycles -- Data Retention: 100 Years -- ESD Protection > 2KV
The X24026 is a CMOS 2048 bit serial E2PROM, internally organized 256 x 8. The X24026 features a serial interface and software protocol allowing operation on a simple two wire bus. Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Available in DICE form, smart card module with ISO 7816 compatible pinout.
FUNCTIONAL DIAGRAM
VCC VSS START CYCLE SDA START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER +COMPARATOR XDEC E 2 PROM 64 X 32 H.V. GENERATION TIMING & CONTROL
SCL
LOAD
INC
WORD ADDRESS COUNTER R/W YDEC 8 CK PIN DOUT ACK
7020 FRM 01
DATA REGISTER
DOUT
Xicor, Inc. 1998 Patents Pending 7020-1.3 6/15/99 T2/C0/D3 SH
1
Characteristics subject to change without notice
X24026
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Guidelines for Calculating Typical Values of Bus Pull-Up Resistors graph. DIE CONFIGURATION
VSS
VCC
SCL SDA SDA
X24026 Die Revision A .055 x .079
7020 FRM 02
PIN DESCRIPTIONS Symbol
SDA SCL VSS VCC
Description
Serial Data Serial Clock Ground +5V
7020 FRM T01
PIN CONFIGURATION
Smart Card Module
V CC NC SCL
V SS NC SDA
35mm TAPE
2
X24026
DEVICE OPERATION The X24026 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X24026 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24026 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
7020 FRM 03
3
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