|
Details, datasheet, quote on part number:X24042S8M-2.7
| |
Datasheet text preview:
Preliminary Information
Pin 7 No X24042 Connect 4K
X24042
Serial E2PROM
DESCRIPTION
512 x 8 Bit
TYPICAL FEATURES
· ·
· · · · · ·
2.7V to 5.5V Power Supply Low Power CMOS --Active Read Current Less Than 1 mA --Active Write Current Less Than 3 mA --Standby Current Less Than 50 µA Internally Organized 512 x 8 2 Wire Serial Interface --Bidirectional Data Transfer Protocol Sixteen Byte Page Write Mode --Minimizes Total Write Time Per Byte Self Timed Write Cycle --Typical Write Cycle Time of 5 ms High Reliability --Endurance: 100,000 Cycles --Data Retention: 100 Years 8 Pin Mini-DlP and 8 Pin SOIC Packages
The X24042 is a CMOS 4,096 bit serial E2PROM, internally organized 512 x 8. The X24042 features a serial interface and software protocol allowing operation on a simple two wire bus. The X24042 is fabricated with Xicor's advanced CMOS Textured Poly Floating Gate Technology. The X24042 utilizes Xicor's proprietary Direct WriteTM cell providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
(8) VCC (4) VSS (5) SDA START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER +COMPARATOR XDEC E2PROM 32 X 128
START CYCLE
H.V. GENERATION TIMING & CONTROL
(6) SCL (3) A2 (2) A1 (1) A0
LOAD
INC
WORD ADDRESS COUNTER R/W YDEC 8 CK PIN DOUT ACK
3849 FHD F01
DATA REGISTER
DOUT
© Xicor, 1991 Patents Pending
3849-1
1
Characteristics subject to change without notice
X24042
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up Resistor selection graph at the end of this data sheet. Address (A0) A0 is unused by the X24042, however, it must be tied to VSS to insure proper device operation. Address (A1, A2) The Address inputs are used to set the appropriate bits of the seven bit slave address. These inputs can be used static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If driven they must be driven to VSS or to VCC.
A0 A1 A2 VSS 1 2 3 4 X24042
PIN CONFIGURATION DIP/SOIC
8 7 6 5 VCC NC SCL SDA
3849 FHD F02
PIN NAMES Symbol A0A2 SDA SCL NC VSS VCC Description Address Inputs Serial Data Serial Clock No Connect Ground Supply Voltage
3849 PGM T01
2
X24042
DEVICE OPERATION The X24042 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24042 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Figure 1. Data Validity Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24042 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24042 to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.
SCL
SDA DATA STABLE DATA CHANGE
3849 FHD F06
Figure 2. Definition of Start and Stop
SCL
SDA START BIT STOP BIT
3849 FHD F07
3
|
|
