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Details, datasheet, quote on part number:X24128-1.8
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Datasheet text preview:
Recommended System Management Alternative: X4283 128K
X24128
400kHz 2-Wire Serial EEPROM with Block LockTM
16K x 8 Bit
FEATURES · Save critical data with programmable block lock protection -- Block lock (0, 1/4, 1/2, or all of EEPROM array) -- Software write protection -- Programmable hardware write protect · In circuit programmable ROM mode · 400kHz 2-wire serial interface -- Schmitt trigger input noise suppression -- Output slope control for ground bounce noise elimination · Longer battery life with lower power -- Active read current less than 1mA -- Active write current less than 3mA -- Standby current less than 1µA · 2.5V to 5.5V power supply version · 32 word page write mode -- Minimizes total write time per word · Internally organized 16K x 8 · Bidirectional data transfer protocol · Self-timed write cycle -- Typical write cycle time of 5ms · High reliability -- Endurance: 100,000 cycles -- Data retention: 100 years · 8-lead XBGA · 14-lead SOIC
DESCRIPTION The X24128 is a CMOS Serial EEPROM, internally organized 16K x 8. The device features a serial interface and software protocol allowing operation on a simple two wire bus. Three device select inputs (S0S2) allow up to eight devices to share a common two wire bus. A Write Protect Register at the highest address location, FFFFh, provides three write protection features: Software Write Protect, Block Lock Protect, and Programmable Hardware Write Protect. The software write protect feature prevents any nonvolatile writes to the device until the WEL bit in the write protect register is set. The Block Lock protection feature gives the user four array block protect options, set by programming two bits in the write protect register. The programmable hardware write protect feature allows the user to install the device with WP tied to VCC, write to and Block Lock the desired portions of the memory array in circuit, and then enable the In Circuit Programmable ROM Mode by programming the WPEN bit HIGH in the Write Protect Register. After this, the Block Locked portions of the array, including the Write Protect Register itself, are permanently protected from being erased. Xicor EEPROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
BLOCK DIAGRAM
Serial EEPROM Data and Address (SDA) Command Decode and Control Logic Block Lock and Write Protect Control Logic S2 S1 S0 Device Select Logic Write Protect Register Page Decode Logic Data Register Y Decode Logic Serial Eeprom Array 16k X 8 4k X 8 4k X 8
SCL
8k X 8
WP REV 1.1 9/8/00
Write Voltage Control
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Characteristics subject to change without notice.
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X24128
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data sheet. Device Select (S0, S1, S2) The device select inputs (S0, S1, S2) are used to set the first three bits of the 8-bit slave address. This allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS). Write Protect (WP) The Write Protect input controls the Hardware Write Protect feature. When held LOW, Hardware Write Protection is disabled. When this input is held HIGH, and the WPEN bit in the Write Protect Register is set HIGH, the Write Protect Register is protected, preventing changes to the Block Lock protection and WPEN bits. PIN NAMES Symbol
S0, S1, S2 SDA SCL WP VSS VCC NC
S0 S1 NC NC NC S2 VSS
PIN CONFIGURATION
8-Lead XBGA: Top View WP 1 VCC 2 SDA 3 SCL 4 8 S1 7 S0 6 VSS 5 S2
14 Lead SOIC 1 2 3 4 5 6 7 14 13 12 X24128 11 10 9 8 VCC WP NC NC NC SCL SDA
DEVICE OPERATION The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the device will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Description
Device Select Inputs Serial Data Serial Clock Write Protect Ground Supply Voltage No Connect
REV 1.1 9/8/00
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Characteristics subject to change without notice.
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X24128
Figure 1. Data Validity
SCL
SDA Data Stable Data Change
Figure 2. Definition of Start and Stop
SCL
SDA START Bit STOP Bit
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
The device will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the device will respond with an acknowledge after the receipt of each subsequent 8-bit word. In the read mode the device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. If an acknowledge is not detected, the device will terminate further data transmissions. The master must then issue a stop condition to return the device to the standby power mode and place the device into a known state.
REV 1.1 9/8/00
www.xicor.com
Characteristics subject to change without notice.
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