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Details, datasheet, quote on part number:X24512
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Datasheet text preview:
Preliminary 256K
X24257
400KHz 2-Wire Serial E2PROM with Block LockTM
32K x 8Bit
FEATURES · Save Critical Data with Programmable Block Lock Protection -- Block Lock (first page, first 2 pages, first 4 pages, first 8 pages, 1/4, 1/2, or all of E2PROM Array) -- Software Write Protection -- Programmable Hardware Write Protect · In Circuit Programmable ROM Mode · 400KHz 2-Wire Serial Interface -- Schmitt Trigger Input Noise Suppression -- Output Slope Control for Ground Bounce Noise Elimination · Longer Battery Life With Lower Power -- Active Read Current Less Than 1mA -- Active Write Current Less Than 3mA -- Standby Current Less Than 1µA · 1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power Supply Versions · 64 Byte Page Write Mode -- Minimizes Total Write Time Per Word · Internally Organized 32K x 8 · Bidirectional Data Transfer Protocol · Self-Timed Write Cycle -- Typical Write Cycle Time of 5ms · High Reliability -- Endurance: 100,000 Cycles -- Data Retention: 100 Years · 8-Lead XBGA, 8-Lead SOIC, 14-Lead TSSOP FUNCTIONAL DIAGRAM
DESCRIPTION The X24257 is a CMOS Serial E2PROM, internally organized 32K x 8. The device features a serial interface and software protocol allowing operation on a simple two wire bus. Three device select inputs (S0S2) allow up to eight devices to share a common two wire bus. A Write Protect Register at the highest address location, FFFFh, provides three write protection features: Software Write Protect, Block Lock Protect, and Programmable Hardware Write Protect. The Software Write Protect feature prevents any nonvolatile writes to the device until the WEL bit in the Write Protect Register is set. The Block Lock Protection feature gives the user eight array block protect options, set by programming three bits in the Write Protect Register. The Programmable Hardware Write Protect feature allows the user to install the device with WP tied to VCC, write to and Block Lock the desired portions of the memory array in circuit, and then enable the In Circuit Programmable ROM Mode by programming the WPEN bit HIGH in the Write Protect Register. After this, the Block Locked portions of the array, including the Write Protect Register itself, are protected from being erased if WP is high.
DATA REGISTER SERIAL E2PROM DATA AND ADDRESS (SDA) SCL COMMAND DECODE AND CONTROL LOGIC BLOCK LOCK AND WRITE PROTECT CONTROL LOGIC S2 S1 S0 WP WRITE VOLTAGE CONTROL PAGE DECODE LOGIC Y DECODE LOGIC
SERIAL E2PROM ARRAY 32K x 8 WRITE PROTECT REGISTER
DEVICE SELECT LOGIC
©Xicor, Inc. 2000 Patents Pending 9800-5004.1 1/31/00 EP
Characteristics subject to change without notice.
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X24257
Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pullup resistor selection graph at the end of this data sheet. Device Select (S0, S1, S2) The device select inputs (S0, S1, S2) are used to set bits in the slave address. This allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS) and they must be constant between each start and stop issued on the SDA bus. These pins have an active pull down internally and will be sensed as low if the pin is left unconnected. Write Protect (WP) WP must be constant between each start and stop issued on the SDA bus and is always active (not gated). The WP pin has an active pull down to disable the write protection when the input is left floating. The Write Protect input controls the Hardware Write Protect feature. When held LOW, Hardware Write Protection is disabled. When this input is held HIGH, and the WPEN bit in the Write Protect Register is set HIGH, the Write Protect Register is protected, preventing changes to the Block Lock Protection and WPEN bits. PIN NAMES Symbol
S0, S1, S2 SDA SCL WP VSS VCC NC
Description
Device Select Inputs Serial Data Serial Clock Write Protect Ground Supply Voltage No Connect
PIN CONFIGURATION
8-Lead XBGA: Top View WP VCC SDA SCL 1 2 3 4 8 7 6 5 S1 S0 VSS S2
14 Lead TSSOP S0 S1 NC NC NC S2 VSS 1 2 3 4 5 6 7 14 13 12 X24257 11 10 9 8 VCC WP NC NC NC SCL SDA
8 Lead PDIP/SOIC S0 S1 S2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
X24257
Characteristics subject to change without notice.
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X24257
DEVICE OPERATION The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the device will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reser ved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
Figure 2. Definition of Start and Stop
SCL
SDA START BIT STOP BIT
Characteristics subject to change without notice.
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