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Details, datasheet, quote on part number:X24C02-3
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Datasheet text preview:
Recommended System Management Alternative: X4043 2K
X24C02
Serial EEPROM
256 x 8 Bit
FEATURES · 2.7V to 5.5V power supply versions · Low power CMOS -- Active read current less than 1 mA -- Active write current less than 1.5 mA · Internally organized 256 x 8 · 2-wire serial interface -- Bidirectional data transfer protocol -- Schmitt trigger input noise suppression 400kHz across VCC range · Sixteen byte page write mode -- Minimizes total write time per byte · Self-timed write cycle -- Typical write cycle time of 5 ms · High reliability -- Endurance: 1,000,000 cycles -- Data retention: 100 years · 8-pin SOIC
DESCRIPTION
BLOCK DIAGRAM
(8) VCC (4) VSS (7) WP
(5) SDA
(6) SCL
(3) A2 (2) A1 (1) A0
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START Cycle START STOP Logic H. V. Generation Timing & Control Control Logic Slave Address Register +Comparator Load INC X Dec EEPROM 16 X 128 Word Address Counter R/W Y Dec 8 CK Pin DOUT ACK Data Register DOUT
The X24C02 is a CMOS 2048 bit serial EEPROM, internally organized 256 x 8. The X24C02 features a serial interface and software protocol allowing operation on a simple two wire bus. The X24C02 is fabricated with Xicor's advanced CMOS Textured Poly Floating Gate Technology. The X24C02 utilizes Xicor's proprietary DirectWriteTM cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years.
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Characteristics subject to change without notice.
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X24C02
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. PIN CONFIGURATION
SOIC A0 A1 A2 1 2 3 4 X24C02 8 7 6 5 VCC WC SCL
An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up Resistor selection graph at the end of this data sheet. Address (A0, A1, A2) The Address inputs (A0, A1, A2) are used to set the appropriate bits of the seven bit slave address. These inputs can be used static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If driven they must be driven to VSS or to VCC. PIN NAMES
Symbol
A0A2 SDA SCL WC VSS VCC
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VSS SDA
DEVICE OPERATION
The X24C02 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24C02 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C02 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Description
Address Inputs Serial Data Serial Clock
Write Control Ground
Supply Voltage
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Characteristics subject to change without notice.
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X24C02
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the Figure 1. Data Validity X24C02 to place the device in the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus.
Figure 2. Definition of Start and Stop
Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
The X24C02 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24C02 will respond with an acknowledge after the receipt of each subsequent eight bit word.
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SCL SDA Data Stable Data Change SCL SDA START Bit STOP Bit
In the read mode the X24C02 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C02 will continue to transmit data. If an acknowledge is not detected, the X24C02 will terminate further data transmissions. The master must then issue a stop condition to return the X24C02 to the standby power mode and place the device into a known state.
www.xicor.com
Characteristics subject to change without notice.
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