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Part: X24F016PE-5
Category:
Memory
-> Flash
Description: Serialflash Memory With Block Lock Protection
Company: Xicor, Inc.
Datasheet: Download X24F016PE-5 datasheet File size : 1333 kB
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Datasheet text preview:
APPLICATION NOTE A V A I LABLE
AN76 · AN78 · AN81 · AN87
64K/32K/16K
X24F064/032/016
8K/4K/2K x 8 Bit
SerialFlashTM Memory with Block LockTM Protection
FEATURES · 1.8V to 3.6V or 5V "Univolt" Read and Program Power Supply Versions · Low Power CMOS -- Active read current less than 1mA -- Active program current less than 3mA -- Standby current less than 1µA · Internally Organized 8K/4K/2K x 8 · New Programmable Block Lock Protection -- Software write protection -- Programmable hardware write protect · Block Lock (0, 1/4, 1/2, or all of the Flash Memory Array) · 2 Wire Serial Interface · Bidirectional Data Transfer Protocol · 32 Byte Sector Programming · Self Timed Program Cycle -- Typical programming time of 5ms per sector · High Reliability -- Endurance: 100,000 cycles per byte -- Data retention: 100 years · Available Packages -- 8-lead PDIP -- 8-lead SOIC (JEDEC) -- 14-lead TSSOP (X24F032/016) -- 20-lead TSSOP (X24F064) DESCRIPTION The X24F064/032/016 is a CMOS SerialFlash Memory Family, internally organized 8K/4K/2K x 8. The family features a serial interface and software protocol allowing operation on a simple two wire bus. Device select inputs (S0, S1, S2) allow up to eight devices to share a common two wire bus. A Program Protect Register accessed at the highest address location, provides three new programming protection features: Software Programming Protection, Block Lock Protection, and Hardware Programming Protection. The Software Programming Protection feature prevents any nonvolatile writes to the device until the WEL bit in the program protect register is set. The Block LockTM Protection feature allows the user to individually protect four blocks of the array by programming two bits in the programming protect register. The Programmable Hardware Program Protect feature allows the user to install each device with PP tied to VCC, program the entire memory array in place, and then enable the hardware programming protection by programming a PPEN bit in the program protect register. After this, selected blocks of the array, including the program protect register itself, are permanently protected from being programmed. Xicor SerialFlash Memories are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.
BLOCK DIAGRAM
SDA SCL X Decode Logic Sectored Memory Array Program Protect Register Data Register Sector Decode Logic 32 Command Decode and Control Logic 8
S0/S0 S1/S1 S2/S2
PP
SerialFlashTM Memory and Block LockTM Protection are trademarks of Xicor, Inc. ©Xicor, Inc. 2000 Patents Pending 6686-3.8 10/27/00 EP
Programming Control Logic
High Voltage Control
Characteristics subject to change without notice.
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X24F064/032/016
PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the pull-up resistor selection graph at the end of this data sheet. Device Select (S0, S0, S1, S1, S2, S2) The device select inputs are used to set the device select bits of the 8-bit slave address. This allows multiple devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS). Program Protect (PP) The program protect input controls the hardware program protect feature. When held LOW, hardware program protection is disabled and the X24F064/032/ 016 can be programmed normally. When this input is held HIGH, and the PPEN bit in the program protect register is set HIGH, program protection is enabled, and nonvolatile writes are disabled to the selected blocks as well as the program protect register itself. PIN NAMES Symbol
S0, S0, S1, S1, S2, S2 SDA SCL PP VSS VCC NC
8-Lead DIP & SOIC S0 S1 S2 VSS 1 2 3 4 8 7 6 5 VCC PP SCL SDA S0 S1 NC NC NC S2 VSS S0 S1 S2 VSS
PIN CONFIGURATION X24F016
8-Lead DIP & SOIC 1 2 3 4 8 7 6 5 VCC PP SCL SDA S0 S1 NC NC NC S2 VSS 14-Lead TSSOP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC PP NC NC NC SCL SDA
X24F032
14-Lead TSSOP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC PP NC NC NC SCL SDA
X24F064
8-Lead DIP & SOIC NC S1 S2 VSS 1 2 3 4 8 7 6 5 VCC PP SCL SDA NC NC S1 NC NC NC S2 NC NC NC 20-Lead TSSOP 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PP VCC PP NC NC NC SCL SCL NC NC
Description
Device Select Inputs Serial Data Serial Clock Program Protect Ground Supply Voltage No Connect
Characteristics subject to change without notice.
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X24F064/032/016
DEVICE OPERATION The X24F064/032/016 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24F064/032/016 will be considered a slave in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reser ved for indicating start and stop conditions. Refer to Figures 1 and 2. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24F064/032/016 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA Data Stable Data Change
Figure 2. Definition of Start and Stop
SCL
SDA START Bit STOP Bit
Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the bus. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3.
The X24F064/032/016 will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the X24F064/032/016 will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the X24F064/032/016 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24F064/ 032/016 will continue to transmit data. If an acknowledge is not detected, the device will terminate further data transmissions. The master must then issue a stop condition to return the X24F064/032/016 to the standby power mode and place the device into a known state.
Characteristics subject to change without notice.
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