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Details, datasheet, quote on part number:X25045SI
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Datasheet text preview:
APPLICATION NOTES
AVAILABLE
A X25043/45 N11 · AN21
4K
X25043/45
Programmable Watchdog Supervisory E2PROM
DESCRIPTION
512 x 8 Bit
FEATURES
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Programmable Watchdog Timer Low VCC Detection Reset Signal Valid to VCC = 1V 1MHz Clock Rate 512 X 8 Bits Serial E2PROM --4 Byte Page Mode Low Power CMOS --50µA Standby Current --3mA Active Current 2.7V To 5.5V Power Supply Block LockTM --Protect 1/4, 1/2 or all of E2PROM Array Built-in Inadvertent Write Protection --Power-Up/Power-Down protection circuitry --Write Latch --Write Protect Pin High Reliability --Endurance: 100,000 cycles per byte --Data Retention: 100 Years --ESD protection: 2000V on all pins Available Packages --8-Lead PDlP --8-Lead SOIC --14-Lead TSSOP X25043 = Active LOW RESET X25045 = Active HIGH RESET
The X25043/45 combines three popular functions, Watchdog Timer, Voltage Supervision, and E2PROM in a single package. This combination lowers the system cost and reduces the board space requirements. The Watchdog Timer provides an independent protection system for microcontrollers. During a system failure, the X25043/45 watchdog will respond with a RESET/ RESET signal after a selectable time-out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The system is protected from low voltage conditions by the X25043/45 low VCC detection circuits. When VCC drops below the minimum VCC trip point, the system is reset. Reset is asserted until VCC returns and stabilizes. The memory portion of the X25043/45 is a CMOS 4096bit serial E2PROM, internally organized as 512 X 8. The X25043/45 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The X25043/45 utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles per byte and a minimum data retention of 100 years.
DIE PHOTOGRAPH
RESET CONTROL LOGIC
PROGRAMMABLE VOLTAGE SENSOR
SERIAL INTERFACE LOGIC
2 4K BITS E2PROM
W AT TI CM HE DR O G
HIIGH VOLTAGE GENERATOR H GH VOLTAGE GENERATOR AND AND CONTROL CONTROL
Direct WriteTM is a trademark of Xicor, Inc. ©Xicor, Inc. 1994, 1995, 1996 Patents Pending 3844-6.5 5/9/96 T4/C2/D2 NS 3844 ILL F01 Characteristics subject to change without notice
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X25043/45
PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25043/45 is deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X25043/45 will be in the standby power mode. CS LOW enables the X25043/45, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW, nonvolatile writes to the X25043/45 are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25043/45. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write. Reset (RESET, RESET) X25043/45, RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the mimimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either HIGH or LOW longer than the Watchdog time-out period. A falling edge of CS will reset the watchdog timer.
CS SO NC NC NC WP VSS X25043/45 8-LEAD DIP/SOIC CS SO WP VSS 1 2 3 4 8 7 6 5 VCC RESET/RESET SCK SI
PIN CONFIGURATION
X25043/45 14-LEAD TSSOP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RESET/RESET NC NC NC SCK SI
3844 ILL F02.3
PIN NAMES Symbol CS SO SI SCK WP VSS VCC RESET/RESET Description Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Reset Output
3844 PGM T01.1
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X25043/45
PRINCIPLES OF OPERATION The X25043/45 is a 512 x 8 designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families. The X25043/45 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be LOW and WP input must be HIGH during the entire operation. The X25043/45 monitors the bus and provides a RESET/RESET output if there is no bus activity within the preset time period. Table 1 contains a list of the instructions and their operation codes. All instructions, addresses and data are transferred MSB first. Bit 3 of the Read and Write instructions contain the higher order address bit, A8. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then resume operations. Write Enable Latch The X25043/45 contains a "write enable" latch. This latch must be SET before a write operation will be completed internally. The WREN instruction will set the latch and the WRDI instruction will reset the latch. This latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status register write cycle. The latch is also reset if WP is brought LOW. Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows: 7 X 6 5 4 X WD1 WD0 3 BL1 2 BL0 1 WEL 0 WIP E2PROM The Write-In-Process (WIP) bit indicates whether the X25043/45 is busy with a write operation. When set to a "1", a write is in progress, when set to a "0", no write is in progress. During a write, all other bits are set to "1". The WIP bit is read-only. The Write Enable Latch (WEL) bit indicates the status of the "write enable" latch. When set to a "1", the latch is set, when set to a "0", the latch is reset. The WEL bit is readonly and is set by the WREN instruction and reset by WRDI instruction or successful completion of a write cycle. The Block Protect (BL0 and BL1) bits indicate the extent of protection employed. These nonvolatile bits are set by issuing the WRSR instruction and allows the user to select one of four levels of protection and program the watchdog timer. The X25043/45 is divided into four 1024-bit segments. One, two, or all four of the segments may be locked. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated below with the state of BL1 and BL0. Status Register Bits BL1 BL0 0 0 1 1 0 1 0 1 Array Addresses Protected None $180$1FF $100$1FF $000$1FF
3844 PGM T04
The Watchdog Timer (WD0 and WD1) bits allow setting of the watchdog time-out function as shown in the table below. These nonvolatile bits are set by issuing the WRSR instruction. Status Register Bits WD1 WD0 0 0 1 1 0 1 0 1 Watchdog Time-out (Typical) 1.4 Seconds 600 Milliseconds 200 Milliseconds Disabled
3844 PGM T03
3844 PGM T02
When issuing, WREN, WRDI and RDSR commands, it is not necessary to send a byte address or data.
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