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Details, datasheet, quote on part number:X25330S8I
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Datasheet text preview:
32K
X25330
5MHz SPI Serial E2PROM with Block LockTM Protection
4K x 8 Bit
FEATURES
DESCRIPTION The X25330 is a CMOS 32K-bit serial E2PROM, internally organized as 4K x 8. The X25330 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25330 also features two additional inputs that provide the end user with added flexibility. By asser ting the HOLD input, the X25330 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25330 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25330 utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
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5MHz Clock Rate Low Power CMOS <1mA Standby Current <5mA Active Current 2.5V To 5.5V Power Supply SPI Modes (0,0 & 1,1) 4K X 8 Bits 32 Byte Page Mode Block LockTM Protection Protect 1/4, 1/2 or all of E2PROM Array Programmable Hardware Write Protection In-Circuit Programmable ROM Mode Built-in Inadvertent Write Protection Power-Up/Down protection circuitry Write Enable Latch Write Protect Pin Self-Timed Write Cycle 5ms Write Cycle Time (Typical) High Reliability Endurance: 1 Million cycles Data Retention: 100 Years ESD protection: 2000V on all pins Packages 8-Lead SOIC 14-Lead TSSOP
FUNCTIONAL DIAGRAM
ST TUS A REGISTER WRITE PROTECT LOGIC X DECODE LOGIC 32 32 X 256 SO SI SCK CS HOLD COMMAND DECODE AND CONTROL LOGIC 32 32 X 256 4K BYTE ARRAY
64 64 X 256
WP
WRITE CONTROL AND TIMING LOGIC 32 8 Y DECODE DATA REGISTER
7037 FRM F01
Direct WriteÔ and Block LockÔ Protection is a trademark of Xicor, Inc.
ÓXicor, Inc. 1994 - 1997 Patents Pending 70481.0 2/12/99 T0/C0/D0 SH 1
Characteristics subject to change without notice
X25330
PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25330 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25330 will be in the standby power mode. CS LOW enables the X25330, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW and the nonvolatile bit WPEN is "1", nonvolatile writes to the X25330 status register are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the PIN NAMES Symbol CS
SO SI SCK
0.200" Max
X25330 status register. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write. The WP pin function is blocked when the WPEN bit in the status register is "0". This allows the user to install the X25330 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set "1". Hold (HOLD) HOLD is used in conjunction with the CS pin to pause the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause
PIN CONFIGURATION
NOT TO SCALE
SOIC CS 0.197" Max SO WP V SS 1 2 3 4 0.244" X25330 8 7 6 5 V CC HOLD SCK SI
TSSOP CS SO SO NC NC WP VSS 1 2 3 14 13 12 VCC HOLD HOLD NC NC SCK SI
Description
Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Hold Input No Connect
7037 FRM T01
4 X25330 11 5 10 6 9 7 0.252" 8
7037 FRM F02
WP
VSS VCC
HOLD
NC
* Pin 2 and Pin 3 are internally connected. Only one CS needs to be connected externally.
2
X25330
the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. PRINCIPLES OF OPERATION The X25330 is a 4K x 8 E2PROM designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families. The X25330 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be LOW and the HOLD and WP inputs must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then resume operations. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input to place the X25330 into a "PAUSE" condition. After releasing HOLD, the X25330 will resume operation from the point when HOLD was first asserted. Write Enable Latch The X25330 contains a "write enable" latch. This latch must be SET before a write operation will be completed internally. The WREN instruction will set the latch and the WRDI instruction will reset the latch. This latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status register write cycle. Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows:
7 WPEN 6 X 5 X 4 X 3 BL1 2 BL0 1 WEL 0 WIP
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WPEN, BL0 and BL1 are set by the WRSR instruction. WEL and WIP are read-only and automatically set by other operations. The Write-In-Process (WIP) bit indicates whether the X25330 is busy with a write operation. When set to a "1", a write is in progress, when set to a "0", no write is in progress. During a write, all other bits are set to "1". The Write Enable Latch (WEL) bit indicates the status of the "write enable" latch. When set to a "1", the latch is set, when set to a "0", the latch is reset. The Block Lock (BL0 and BL1) bits are nonvolatile and allow the user to select one of four levels of protection. The X25330 is divided into four 8K bit segments. One, two, or all four of the segments may be protected. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The par titioning is controlled as illustrated below. Status Register Bits BL1
0 0 1 1
BL0
0 1 0 1
Array Addresses Protected
None $0C00$0FFF $0800$0FFF $0000$0FFF
7037 FRM T03
Table 1. Instruction Set Instruction Name
WREN WRDI RDSR WRSR READ WRITE
Instruction Format*
0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Operation
Set the Write Enable Latch (Enable Write Operations) Reset the Write Enable Latch (Disable Write Operations) Read Status Register Write Status Register Read Data from Memory Array beginning at selected address Write Data to Memory Array beginning at Selected Address (1 to 32 Bytes)
7037 FRM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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